AD7770 の電気的特性と機能

AD7770のメーカーはAnalog Devicesです、この部品の機能は「Simultaneous Sampling ADC」です。

製品の詳細 ( Datasheet PDF )

部品番号
AD7770

部品説明
Simultaneous Sampling ADC

メーカ
Analog Devices

ロゴ

このページの下部にプレビューとAD7770ダウンロード（pdfファイル）リンクがあります。

Total 30 pages

No Preview Available !

Data Sheet

FEATURES

8-channel, 24-bit simultaneous sampling analog-to-digital

converter (ADC)

Single-ended or true differential inputs

Programmable gain amplifier (PGA) per channel (gains of

1, 2, 4, and 8)

Low dc input current: ±8 nA

Up to 32 kSPS output data rate (ODR) per channel

Programmable ODRs and bandwidth

Sample rate converter (SRC) for coherent sampling

Sampling rate resolution up to 15.2 × 10−6 SPS

Low latency sinc3 filter path

Adjustable phase synchronization

Internal 2.5 V reference

Two power modes

High resolution mode

Low power mode

Optimizes power dissipation and performance

Low resolution successive approximation register (SAR) ADC

for system and chip diagnostics

Power supply

Bipolar (±1.65 V) or unipolar (3.3 V) supplies

Digital input/output (I/O) supply: 1.8 V to 3.6 V

Performance temperature range: −40°C to +105°C

Functional temperature range: −40°C to +125°C

Performance

Combined ac and dc performance

103 dB dynamic range at 32 kSPS in high resolution mode

−109 dB total harmonic distortion (THD)

±9 ppm of FSR integral nonlinearity (INL)

±15 µV offset error

±0.1% FS gain error

±10 ppm/°C typical temperature coefficient

APPLICATIONS

Protection relays

General-purpose data acquisition

Industrial process control

GENERAL DESCRIPTION

The AD7770 is an 8-channel, simultaneous sampling ADC. Eight

full sigma-delta (Σ-Δ) ADCs are on chip. The AD7770 provides

a low input current to allow direct sensor connection. Each input

channel has a programmable gain stage allowing gains of 1, 2, 4,

and 8 to map lower amplitude sensor outputs into the full-scale

ADC input range, maximizing the dynamic range of the signal

chain. The AD7770 accepts a VREF voltage from 1 V up to 3.6 V.

Rev. B

Document Feedback

Information furnished by Analog Devices is believed to be accurate and reliable. However, no

responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other

rights of third parties that may result from its use. Specifications subject to change without notice. No

license is granted by implication or otherwise under any patent or patent rights of Analog Devices.

Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.

8-Channel, 24-Bit,

Simultaneous Sampling ADC

AD7770

The analog inputs accept unipolar (0 V to VREF) or true bipolar

(±VREF/2) analog input signals with 3.3 V or ±1.65 V analog

supply voltages, respectively for PGAGAIN = 1. The analog inputs

can accept true differential, pseudo differential, or single-ended

signals to match different sensor output configurations.

Each channel contains a PGA, an ADC modulator and a

sinc3, low latency digital filter. An SRC is provided to allow fine

resolution control over the AD7770 ODR. This control can be

used in applications where the ODR resolution is required to

maintain coherency with 0.01 Hz changes in the line frequency.

The SRC is programmable through the serial port interface (SPI).

The AD7770 implements two different interfaces: a data output

interface and SPI control interface. The ADC data output interface

is dedicated to transmitting the ADC conversion results from

the AD7770 to the processor. The SPI writes to and reads from

the AD7770 configuration registers and for the control and

reading of data from the SAR ADC. The SPI can also be

configured to output the Σ-Δ conversion data.

The AD7770 includes a 12-bit SAR ADC. This ADC can be

used for AD7770 diagnostics without having to decommission

one of the Σ-Δ ADC channels dedicated to system measurement

functions. With the use of an external multiplexer, which can be

controlled through the three general-purpose input/output pins

(GPIOs), and signal conditioning, the SAR ADC can validate

the Σ-Δ ADC measurements in applications where functional

safety is required. In addition, the AD7770 SAR ADC includes

an internal multiplexer to sense internal nodes.

The AD7770 contains a 2.5 V reference and reference buffer. The

reference has a typical temperature coefficient of 10 ppm/°C.

The AD7770 offers two modes of operation: high resolution mode

and low power mode. High resolution mode provides a higher

dynamic range while consuming 10.75 mW per channel; low

power mode consumes just 3.37 mW per channel at a reduced

dynamic range specification.

The specified operating temperature range is −40°C to +105°C,

although the device is operational up to +125°C.

Note that throughout this data sheet, certain terms are used to

refer to either the multifunction pins or a range of pins. The multi-

function pins, such as DCLK0/SDO, are referred to either by the

entire pin name or by a single function of the pin, for example,

DCLK0, when only that function is relevant. In the case of ranges

of pins, AVSSx refers to the following pins: AVSS1A, AVSS1B,

AVSS2A, AVSS2B, AVSS3, and AVSS4.

One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.

Tel: 781.329.4700

Technical Support

www.analog.com

1 Page

AD7770

Data Sheet

TABLE OF CONTENTS

Features .............................................................................................. 1

Applications....................................................................................... 1

General Description ......................................................................... 1

Revision History ............................................................................... 4

Functional Block Diagram .............................................................. 5

Specifications..................................................................................... 6

DOUTx Timing Characterististics........................................... 10

SPI Timing Characterististics ................................................... 11

Synchronization Pins and Reset Timing Characteristics ...... 12

SAR ADC Timing Characterististics ....................................... 13

GPIO SRC Update Timing Characterististics......................... 13

Absolute Maximum Ratings.......................................................... 14

Thermal Resistance .................................................................... 14

ESD Caution................................................................................ 14

Pin Configuration and Function Descriptions........................... 15

Typical Performance Characteristics ........................................... 18

Terminology .................................................................................... 31

Theory of Operation ...................................................................... 33

Analog Inputs.............................................................................. 33

Transfer Function ....................................................................... 34

Core Signal Chain....................................................................... 35

Capacitive PGA........................................................................... 35

Internal Reference and Reference Buffers............................... 35

Integrated LDOs ......................................................................... 36

Clocking and Sampling.............................................................. 36

ADC Conversion Output—Header and Data ........................ 51

SRC (SPI Control Mode)........................................................... 52

Data Output Interface................................................................ 53

Calculating the CRC Checksum .............................................. 58

Channel 0 Configuration Register ........................................... 64

Channel 1 Configuration Register ........................................... 64

Channel 2 Configuration Register ........................................... 65

Channel 3 Configuration Register ........................................... 65

Channel 4 Configuration Register ........................................... 66

Channel 5 Configuration Register ........................................... 66

Channel 6 Configuration Register ........................................... 67

Channel 7 Configuration Register ........................................... 67

Disable Clocks to ADC Channel Register .............................. 68

Channel 0 Sync Offset Register ................................................ 68

Channel 1 Sync Offset Register ................................................ 68

Channel 2 Sync Offset Register ................................................ 68

Channel 3 Sync Offset Register ................................................ 69

Channel 4 Sync Offset Register ................................................ 69

Channel 5 Sync Offset Register ................................................ 69

Channel 6 Sync Offset Register ................................................ 69

Channel 7 Sync Offset Register ................................................ 69

General User Configuration 1 Register................................... 70

General User Configuration 2 Register................................... 70

Digital Reset and Synchronization Pins .................................. 36

Digital Filtering........................................................................... 37

Shutdown Mode.......................................................................... 37

Controlling the AD7770 ............................................................ 38

Pin Control Mode....................................................................... 38

SPI Control .................................................................................. 40

Digital SPI.................................................................................... 43

RMS Noise and Resolution............................................................ 46

High Resolution Mode............................................................... 46

Low Power Mode........................................................................ 46

Diagnostics and Monitoring ......................................................... 47

Self Diagnostics Error...........................................................................47

Monitoring Using the AD7770 SAR ADC (SPI Control Mode)...48

Σ-Δ ADC Diagnostics (SPI Control Mode)....................................50

Σ-Δ Output Data............................................................................. 51

General User Configuration 3 Register................................... 71

Data Output Format Register ................................................... 72

Main ADC Meter and Reference Mux Control Register ...... 73

Global Diagnostics Mux Register............................................. 74

GPIO Configuration Register................................................... 74

GPIO Data Register.................................................................... 75

Buffer Configuration 1 Register ............................................... 75

Buffer Configuration 2 Register ............................................... 75

Channel 0 Offset Upper Byte Register..................................... 76

Channel 0 Offset Middle Byte Register................................... 76

Channel 0 Offset Lower Byte Register..................................... 76

Channel 0 Gain Upper Byte Register....................................... 76

Channel 0 Gain Middle Byte Register ..................................... 76

Channel 0 Gain Lower Byte Register....................................... 77

Channel 1 Offset Upper Byte Register..................................... 77

Rev. B | Page 2 of 97

3Pages

Data Sheet

FUNCTIONAL BLOCK DIAGRAM

AVDD1x REF_OUT REFx+ REFx–

AVDD2 AREGxCAP IOVDD DREGCAP

VCM

AIN0+

AIN0–

AIN1+

AIN1–

AIN2+

AIN2–

AIN3+

AIN3–

AIN4+

AIN4–

AIN5+

AIN5–

AIN6+

AIN6–

AIN7+

AIN7–

AUXAIN+

AUXAIN–

COMMON-

MODE

VOLTAGE

2.5V REF

280mV p-p

EXT_REF

INT_REF

REFERENCES

PGA

DIAGNOSTIC

INPUTS

ANALOG

LDO

DIGITAL

LDO

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

Σ-Δ ADC

SINC3/

SRC

FILTER

GAIN

OFFSET

AND

LOGIC CONTROL

SAR ADC

AVSSx

AVDD4

CONVST_SAR

Figure 1.

AD7770

CLOCK

MANAGER

DATA OUTPUT

INTERFACE

HARDWARE

MODE

CONFIGURATION

XTAL1

XTAL2/MCLK

SYNC_IN

SYNC_OUT

START

DCLK

DRDY

DOUT3

DOUT2

DOUT1

DOUT0

RESET

FORMAT1

FORMAT0

MODE3/ALERT

MODE2/GPIO2

MODE1/GPIO1

MODE0/GPIO0

SPI INTERFACE

ALERT/CS

DCLK2/SCLK

DCLK1/SDI

DCLK0/SDO

AD7770

Rev. B | Page 5 of 97

6 Page

合計 : 30 ページ

PDF ダウンロード

[ AD7770 データシート.PDF ]

データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。ピン構成、電気的特性、動作パラメータ、性能を確認してください。

部品番号	部品説明	メーカ
AD7770	Simultaneous Sampling ADC	Analog Devices
AD7773	EMVEDDED SERVO FRONT ENDS	Analog Devices
AD7774	ANALOG I/O PORT	Analog Devices
AD7775	EMVEDDED SERVO FRONT ENDS	Analog Devices

www.DataSheet.jp

|     2020 | メール |

    最新        |     Sitemap