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AD6657A の電気的特性と機能
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AD6657AのメーカーはAnalog Devicesです、この部品の機能は「Quad IF Receiver」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 AD6657A |
| 部品説明 Quad IF Receiver |
| メーカ Analog Devices |
ロゴ |
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Data Sheet
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer
Performance with NSR enabled
SNR: 76.0 dBFS in 40 MHz band to 70 MHz at 185 MSPS
SNR: 73.6 dBFS in 60 MHz band to 70 MHz at 185 MSPS
SNR: 72.8 dBFS in 65 MHz band to 70 MHz at 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz at 185 MSPS
SFDR: 88 dBc to 70 MHz at 185 MSPS
Low power: 1.2 W at 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self test (BIST) capability
Energy saving power-down modes
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
GENERAL DESCRIPTION
The AD6657A is an 11-bit, 200 MSPS, quad channel intermediate
frequency (IF) receiver specifically designed to support multiple
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of four high performance ADCs and NSR
digital blocks. Each ADC consists of a multistage, differential
pipelined architecture with integrated output error correction
logic. The ADC features a wide bandwidth switched capacitor
sampling network within the first stage of the differential pipeline.
An integrated voltage reference eases design considerations. A
duty cycle stabilizer (DCS) compensates for variations in the
ADC clock duty cycle, allowing the converters to maintain
excellent performance.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
Quad IF Receiver
AD6657A
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DRVDD DRGND
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
VIN+C
VIN–C
VCMC
VIN+D
VIN–D
VCMD
AD6657A
PIPELINE 14 NOISE SHAPING 11
ADC
REQUANTIZER
14
PIPELINE
NOISE SHAPING 11
ADC
REQUANTIZER
14 11
PIPELINE
NOISE SHAPING
ADC
REQUANTIZER
14
PIPELINE
NOISE SHAPING 11
ADC
REQUANTIZER
DCO±AB
DO±AB
PORT A
D10±AB
DCO±CD
DO±CD
PORT B
D10±CD
REFERENCE
SERIAL PORT
CLOCK
DIVIDER
MODE
SYNC
PDWN
SCLK SDIO CSB
Figure 1.
CLK+ CLK–
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance in
a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the serial port interface (SPI).
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6657A supports enhanced SNR per-
formance within a limited portion of the Nyquist bandwidth while
maintaining an 11-bit output resolution. The NSR block can be
programmed to provide a bandwidth of either 22%, 33%, or 36% of
the sample clock. For example, with a sample clock rate of
185 MSPS, the AD6657A can achieve up to 76.0 dBFS SNR for a
40 MHz bandwidth in the 22% mode, up to 73.6 dBFS SNR for a
60 MHz bandwidth in the 33% mode, or up to 72.8 dBFS SNR for a
65 MHz bandwidth in the 36% mode.
(General Description continued on Page 3)
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
AD6657A
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Product Highlights ........................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 7
Switching Specifications .............................................................. 9
Timing Specifications ................................................................ 10
Absolute Maximum Ratings ..................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
Equivalent Circuits ......................................................................... 18
Theory of Operation ...................................................................... 19
ADC Architecture ...................................................................... 19
Analog Input Considerations.................................................... 19
Clock Input Considerations ...................................................... 21
Power Dissipation and Standby Mode..................................... 23
REVISION HISTORY
2/14—Rev. 0 to Rev. A
Changed DCO to Data Skew (tSKEW) Parameter Unit from ns to
ps, Table 4 .......................................................................................... 9
10/11—Revision 0: Initial Version
Data Sheet
Channel/Chip Synchronization................................................ 23
Digital Outputs ........................................................................... 24
Timing.......................................................................................... 24
Noise Shaping Requantizer ........................................................... 25
22% BW Mode (>40 MHz at 184.32 MSPS)........................... 25
33% BW Mode (>60 MHz at 184.32 MSPS)........................... 26
36% BW Mode (>65 MHz at 184.32 MSPS)........................... 27
MODE Pin................................................................................... 27
Built-In Self Test (BIST) and Output Test ................................... 28
BIST.............................................................................................. 28
Output Test Modes..................................................................... 28
Serial Port Interface (SPI).............................................................. 29
Configuration Using the SPI..................................................... 29
Hardware Interface..................................................................... 29
Memory Map .................................................................................. 30
Reading the Memory Map Register Table............................... 30
Memory Map Register Table..................................................... 31
Memory Map Register Descriptions........................................ 33
Applications Information .............................................................. 35
Design Guidelines ...................................................................... 35
Packaging and Ordering Information ......................................... 36
Outline Dimensions................................................................... 36
Ordering Guide .......................................................................... 36
Rev. A | Page 2 of 36
3Pages
Data Sheet
AD6657A
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, fS = 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)—NSR DISABLED
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SIGNAL-TO-NOISE-RATIO (SNR)—NSR ENABLED
22% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
33% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 230 MHz
36% BW Mode
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
SIGNAL-TO-NOISE-AND DISTORTION (SINAD)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 10 MHz
fIN = 50 MHz
fIN = 70 MHz
fIN = 170 MHz
fIN = 250 MHz
Temperature Min Typ Max Unit
25°C 66.6
25°C 66.5
25°C 66.5
25°C 66.3
Full 65.6
25°C 65.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C 76.0
25°C 75.7
25°C 75.7
25°C 74.3
Full 72.9
25°C 72.8
25°C 73.6
25°C 73.6
25°C 73.3
25°C 72.5
Full 71.3
25°C 71.2
25°C 72.8
25°C 72.6
25°C 72.6
25°C 71.8
Full 70.7
25°C 70.8
25°C 65.5
25°C 65.5
25°C 65.5
25°C 65.3
Full 64.6
25°C 64.8
25°C 10.6
25°C 10.6
25°C 10.6
25°C 10.6
25°C 10.5
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Bits
Bits
Bits
Bits
Bits
Rev. A | Page 5 of 36
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| AD6657 | Quad IF Receiver | Analog Devices |
| AD6657A | Quad IF Receiver | Analog Devices |