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SSM2604 の電気的特性と機能
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SSM2604のメーカーはAnalog Devicesです、この部品の機能は「Low Power Audio Codec」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 SSM2604 |
| 部品説明 Low Power Audio Codec |
| メーカ Analog Devices |
ロゴ |
このページの下部にプレビューとSSM2604ダウンロード（pdfファイル）リンクがあります。 Total 29 pages |
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Data Sheet
Low Power Audio Codec
SSM2604
FEATURES
GENERAL DESCRIPTION
Stereo, 24-bit analog-to-digital and digital-to-analog converters
DAC SNR: 100 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
ADC SNR: 90 dB (A-weighted), THD: −80 dB at 48 kHz, 3.3 V
Stereo line inputs
Low power
7 mW stereo playback (1.8 V/1.5 V supplies)
14 mW record and playback (1.8 V/1.5 V supplies)
Low supply voltages
Analog: 1.8 V to 3.6 V
Digital: 1.5 V to 3.6 V
256/384 oversampling rate in normal mode;
250/272 oversampling rate in USB mode
Audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz,
22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz,
and 96 kHz
20-lead, 4 mm × 4 mm LFCSP (QFN) package
APPLICATIONS
Mobile phones
MP3 players
Portable gaming
Portable electronics
Educational toys
The SSM2604 is a low power, high quality stereo audio codec
for portable digital audio applications with one set of stereo
programmable gain amplifier (PGA) line inputs. It features two
24-bit analog-to-digital converter (ADC) channels and two
24-bit digital-to-analog (DAC) converter channels.
The SSM2604 can operate as a master or a slave. It supports
various master clock frequencies, including 12 MHz or 24 MHz
for USB devices; standard 256 fS or 384 fS based rates, such as
12.288 MHz and 24.576 MHz; and many common audio sam-
pling rates, such as 96 kHz, 88.2 kHz, 48 kHz, 44.1 kHz, 32 kHz,
24 kHz, 22.05 kHz, 16 kHz, 12 kHz, 11.025 kHz, and 8 kHz.
The SSM2604 can operate at power supplies as low as 1.8 V for
the analog circuitry and as low as 1.5 V for the digital circuitry.
The maximum voltage supply is 3.6 V for all supplies.
The SSM2604 is specified over the industrial temperature range
of −40°C to +85°C. It is available in a 20-lead, 4 mm × 4 mm
lead frame chip scale package (LFCSP).
FUNCTIONAL BLOCK DIAGRAM
AVDD VMID AGND
DVDD DGND
BYPASS
SSM2604
–34.5dB TO +33dB,
1.5dB STEP
RLINEIN
ADC
DAC
ROUT
DIGITAL
PROCESSOR
LLINEIN
–34.5dB TO +33dB,
1.5dB STEP
ADC
DAC
LOUT
CLK
BYPASS
DIGITAL AUDIO INTERFACE
CONTROL INTERFACE
MCLK/ XTO CLKOUT
XTI
PBDAT RECDAT BCLK PBLRC RECLRC SDIN
Figure 1.
SCLK
Rev. A
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
SSM2604
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Digital Filter Characteristics ....................................................... 4
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Converter Filter Response........................................................... 9
Digital De-Emphasis .................................................................. 10
Theory of Operation ...................................................................... 11
Digital Core ................................................................................. 11
ADC and DAC............................................................................ 11
ADC High-Pass and DAC De-Emphasis Filters .................... 11
REVISION HISTORY
6/13—Rev. 0 to Rev. A
Changes to Table 8.............................................................................7
Added Control Register Sequencing Section...............................15
Updated Outline Dimensions ........................................................26
7/08—Revision 0: Initial Version
Data Sheet
Analog Interface ......................................................................... 12
Digital Audio Interface .............................................................. 12
Software Control Interface........................................................ 15
Control Register Sequencing .................................................... 15
Typical Application Circuits ......................................................... 16
Register Map ................................................................................... 17
Register Map Details ...................................................................... 18
Left-Channel ADC Input Volume, Address 0x00.................. 18
Right-Channel ADC Input Volume, Address 0x01 ............... 19
Analog Audio Path, Address 0x04 ........................................... 20
Digital Audio Path, Address 0x05 ............................................ 20
Power Management, Address 0x06.......................................... 21
Digital Audio I/F, Address 0x07 ............................................... 22
Sampling Rate, Address 0x08.................................................... 22
Active, Address 0x09.................................................................. 25
Software Reset, Address 0x0F................................................... 25
Outline Dimensions ....................................................................... 26
Ordering Guide .......................................................................... 26
Rev. A | Page 2 of 28
3Pages
Data Sheet
TIMING CHARACTERISTICS
Table 3. I2C Timing
Parameter
tSCS
tSCH
tPH
tPL
fSCLK
tDS
tDH
tRT
tFT
tHCS
tMIN
600
600
600
1.3
0
100
600
Limit
tMAX
526
900
300
300
SDIN
SCLK
Unit Description
ns Start condition setup time
ns Start condition hold time
ns SCLK pulse width high
μs SCLK pulse width low
kHz SCLK frequency
ns Data setup time
ns Data hold time
ns SDIN and SCLK rise time
ns SDIN and SCLK fall time
ns Stop condition setup time
tSCH
tPL tDS
tPH
tRT tDH tFT
Figure 2. I2C Timing
tHCS
tSCS
SSM2604
Table 4. Digital Audio Interface Slave Mode Timing
Limit
Parameter
tMIN
tMAX Unit
tDS 10
ns
tDH 10
ns
tLRSU
10
ns
tLRH 10
ns
tDD 30 ns
tBCH 25
ns
tBCL 25
ns
tBCY 50
ns
Description
PBDAT setup time from BCLK rising edge
PBDAT hold time from BCLK rising edge
RECLRC/PBLRC setup time to BCLK rising edge
RECLRC/PBLRC hold time to BCLK rising edge
RECDAT propagation delay from BCLK falling edge (external load of 70 pF)
BCLK pulse width high
BCLK pulse width low
BCLK cycle time
tBCH tBCL
BCLK
tBCY
PBLRC/
RECLRC
tDS tLRH tLRSU
PBDAT
RECDAT
tDD tDH
Figure 3. Digital Audio Interface Slave Mode Timing
Rev. A | Page 5 of 28
6 Page
合計 : 29 ページ |
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| 部品番号 | 部品説明 | メーカ |
| SSM2602 | Low Power Audio Codec | Analog Devices |
| SSM2602GY | N-channel Enhancement-mode Power MOSFET |  Silicon Standard |
| SSM2602Y | N-CHANNEL ENHANCEMENT-MODE POWER MOSFET | Silicon Standard |
| SSM2603 | Low Power Audio Codec | Analog Devices |