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ADAU1361 の電気的特性と機能
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ADAU1361のメーカーはAnalog Devicesです、この部品の機能は「24-Bit Audio Codec」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 ADAU1361 |
| 部品説明 24-Bit Audio Codec |
| メーカ Analog Devices |
ロゴ |
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Stereo, Low Power, 96 kHz, 24-Bit
Audio Codec with Integrated PLL
ADAU1361
FEATURES
GENERAL DESCRIPTION
24-bit stereo audio ADC and DAC: >98 dB SNR
Sampling rates from 8 kHz to 96 kHz
Low power: 7 mW record, 7 mW playback, 48 kHz at 1.8 V
6 analog input pins, configurable for single-ended or
differential inputs
Flexible analog input/output mixers
Stereo digital microphone input
Analog outputs: 2 differential stereo, 2 single-ended stereo,
1 mono headphone output driver
PLL supporting input clocks from 8 MHz to 27 MHz
Analog automatic level control (ALC)
Microphone bias reference voltage
Analog and digital I/O: 1.8 V to 3.65 V
I2C and SPI control interfaces
Digital audio serial data I/O: stereo and time-division
multiplexing (TDM) modes
Software-controllable clickless mute
Software power-down
32-lead, 5 mm × 5 mm LFCSP
−40°C to +85°C operating temperature range
APPLICATIONS
Smartphones/multimedia phones
Digital still cameras/digital video cameras
Portable media players/portable audio players
Phone accessories products
The ADAU1361 is a low power, stereo audio codec that supports
stereo 48 kHz record and playback at 14 mW from a 1.8 V analog
supply. The stereo audio ADCs and DACs support sample rates
from 8 kHz to 96 kHz as well as a digital volume control. The
ADAU1361 is ideal for battery-powered audio and telephony
applications.
The record path includes an integrated microphone bias circuit
and six inputs. The inputs can be mixed and muxed before the
ADC, or they can be configured to bypass the ADC. The
ADAU1361 includes a stereo digital microphone input.
The ADAU1361 includes five high power output drivers (two
differential and three single-ended), supporting stereo head-
phones, an earpiece, or other output transducer. AC-coupled
or capless configurations are supported. Individual fine level
controls are supported on all analog outputs. The output mixer
stage allows for flexible routing of audio.
The serial control bus supports the I2C and SPI protocols. The
serial audio bus is programmable for I2S, left-/right-justified,
and TDM modes. A programmable PLL supports flexible clock
generation for all standard integer rates and fractional master
clocks from 8 MHz to 27 MHz.
FUNCTIONAL BLOCK DIAGRAM
JACKDET/MICIN
HP JACK REGULATOR
DETECTION
ADAU1361
LAUX
LINP
LINN
RINP
RINN
RAUX
INPUT
MIXERS
ALC
ADC
ADC
ADC
DAC
DIGITAL DIGITAL
FILTERS FILTERS
DAC
DAC
OUTPUT
MIXERS
LOUTP
LOUTN
LHP
MONOOUT
RHP
ROUTP
ROUTN
MICBIAS
MICROPHONE
BIAS
PLL
SERIAL DATA
INPUT/OUTPUT PORTS
I2C/SPI
CONTROL PORT
MCLK ADC_SDATA
DAC_SDATA ADDR0/ ADDR1/ SCL/ SDA/
CLATCH CDATA CCLK COUT
Figure 1.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2009–2010 Analog Devices, Inc. All rights reserved.
1 Page
ADAU1361
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications ........................................... 4
Power Supply Specifications........................................................ 7
Typical Current Consumption.................................................... 8
Typical Power Management Measurements ............................. 9
Digital Filters............................................................................... 10
Digital Input/Output Specifications......................................... 10
Digital Timing Specifications ................................................... 11
Digital Timing Diagrams........................................................... 12
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 20
Theory of Operation ...................................................................... 23
Startup, Initialization, and Power ................................................. 24
Power-Up Sequence ................................................................... 24
Power Reduction Modes............................................................ 24
Digital Power Supply.................................................................. 24
Input/Output Power Supply...................................................... 24
Clock Generation and Management........................................ 24
Clocking and Sampling Rates ....................................................... 26
Core Clock................................................................................... 26
Sampling Rates............................................................................ 26
PLL ............................................................................................... 27
Record Signal Path ......................................................................... 29
Input Signal Paths....................................................................... 29
Analog-to-Digital Converters................................................... 31
Automatic Level Control (ALC)................................................... 32
ALC Parameters.......................................................................... 32
Noise Gate Function .................................................................. 33
Playback Signal Path ...................................................................... 35
Output Signal Paths ................................................................... 35
Headphone Output .................................................................... 36
Pop-and-Click Suppression ...................................................... 37
Line Outputs ............................................................................... 37
Control Ports................................................................................... 38
Burst Mode Writing and Reading ............................................ 38
I2C Port ........................................................................................ 38
SPI Port ........................................................................................ 41
Serial Data Input/Output Ports .................................................... 42
Applications Information .............................................................. 44
Power Supply Bypass Capacitors.............................................. 44
GSM Noise Filter ........................................................................ 44
Grounding ................................................................................... 44
Exposed Pad PCB Design ......................................................... 44
Control Registers ............................................................................ 45
Control Register Details ............................................................ 46
Outline Dimensions ....................................................................... 79
Ordering Guide .......................................................................... 79
Rev. C | Page 2 of 80
3Pages
Parameter
PSEUDO-DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Common-Mode Rejection Ratio
FULL DIFFERENTIAL PGA INPUT
Full-Scale Input Voltage (0 dB)
Dynamic Range
With A-Weighted Filter (RMS)
No Filter (RMS)
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio
With A-Weighted Filter (RMS)
No Filter (RMS)
Volume Control Step
Volume Control Range
PGA Boost
Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Test Conditions/Comments
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
100 mV rms, 1 kHz
100 mV rms, 20 kHz
Differential PGA inputs
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
−1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
PGA gain
PGA gain
ADAU1361
Min Typ Max Unit
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
92 dB
98 dB
90 dB
95 dB
−88 dB
−89 dB
92 dB
98 dB
90 dB
95 dB
0.75 dB
−12
+35.25
dB
20 dB
−87 dB
0.005
dB
0 mV
−14 %
83 dB
65 dB
65 dB
AVDD/3.3
0.55 (1.56)
1.0 (2.83)
V rms
V rms (V p-p)
V rms (V p-p)
92 dB
98 dB
90 dB
95 dB
−70 dB
−78 dB
92 dB
98 dB
90 dB
95 dB
0.75 dB
−12
+35.25
dB
20 dB
−87 dB
0.005
dB
0 mV
−14 %
Rev. C | Page 5 of 80
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| ADAU1361 | 24-Bit Audio Codec | Analog Devices |