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ADAU1772 の電気的特性と機能
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ADAU1772のメーカーはAnalog Devicesです、この部品の機能は「Four ADC / Two DAC Low Power Codec」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 ADAU1772 |
| 部品説明 Four ADC / Two DAC Low Power Codec |
| メーカ Analog Devices |
ロゴ |
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Data Sheet
Four ADC, Two DAC Low Power Codec
with Audio Processor
ADAU1772
FEATURES
Programmable audio processing engine
192 kHz processing path
Biquad filters, limiters, volume controls, mixing
Low latency, 24-bit ADCs and DACs
102 dB SNR (signal through PGA and ADC
with A-weighted filter)
107 dB combined SNR (signal through DAC and headphone
with A-weighted filter)
Serial port sample rates from 8 kHz to 192 kHz
38 μs analog-to-analog latency
4 single-ended analog inputs—configurable as microphone
or line inputs
Dual stereo digital microphone inputs
Stereo analog audio output—single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full-duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital I/O of 1.8 V to 3.3 V
Digital signal processing (DSP) core of 1.1 V to 1.8 V
Low power (15 mW for typical noise cancelling solution)
I2C and SPI control interfaces, self-boot from I2C EEPROM
7 MP pins supporting dual stereo digital microphone inputs,
stereo PDM output, mute, DSP bypass, push-button
volume controls, and parameter bank switching
APPLICATIONS
Noise cancelling handsets, headsets, and headphones
Bluetooth ANC handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
GENERAL DESCRIPTION
The ADAU1772 is a codec with four inputs and two outputs that
incorporates a digital processing engine to perform filtering,
level control, signal level monitoring, and mixing. The path
from the analog input to the DSP core to the analog output is
optimized for low latency and is ideal for noise cancelling headsets.
With the addition of just a few passive components, a crystal,
and an EEPROM for booting, the ADAU1772 provides a
complete headset solution.
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
AIN0REF
AIN0
AIN1REF
AIN1
DMIC0_1/MP4
DMIC2_3/MP5
AIN2REF
AIN2
AIN3REF
AIN3
CM
MICROPHONE
BIAS GENERATORS
PGA
ADC
MODULATOR
PGA
ADC
MODULATOR
DIGITAL
MICROPHONE
INPUTS
PGA
ADC
MODULATOR
PGA
ADC
MODULATOR
POWER
MANAGEMENT
LDO
REGULATOR
ADC
DECIMATOR
ADC
DECIMATOR
INPUT/OUTPUT
SIGNAL
ROUTING
ADC
DECIMATOR
ADC
DECIMATOR
DSP CORE:
BIQUAD FILTERS,
LIMITERS,
VOLUME CONTROLS,
MIXING
ADAU1772
PLL
CLOCK
OSCILLATOR
DAC
STEREO PDM
MODULATOR
DAC
BIDIRECTIONAL
ASRCS
SERIAL
INPUT/
OUTPUT
PORT
I2C/SPI CONTROL
INTERFACE AND SELF-BOOT
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
XTALO
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
DAC_SDATA/MP0
ADC_SDATA0/PDMOUT/MP1
BCLK/MP2
LRCLK/MP3
Figure 1.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 Page
ADAU1772
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications ........................................... 4
Crystal Amplifier Specifications................................................. 7
Digital Input/Output Specifications........................................... 8
Power Supply Specifications........................................................ 8
Typical Power Consumption....................................................... 9
Digital Filters................................................................................. 9
Digital Timing Specifications ................................................... 10
Absolute Maximum Ratings.......................................................... 14
Thermal Resistance .................................................................... 14
ESD Caution................................................................................ 14
Pin Configuration and Function Descriptions........................... 15
Typical Performance Characteristics ........................................... 17
System Block Diagrams ................................................................. 28
Theory of Operation ...................................................................... 29
System Clocking and Power-Up................................................... 30
Clock Initialization..................................................................... 30
PLL ............................................................................................... 30
Clock Output............................................................................... 31
Power Sequencing ...................................................................... 31
Signal Routing................................................................................. 32
Input Signal Paths........................................................................... 33
Analog Inputs.............................................................................. 33
Digital Microphone Input ......................................................... 34
Analog-to-Digital Converters................................................... 34
Output Signal Paths........................................................................ 35
Analog Outputs........................................................................... 35
Digital-to-Analog Converters................................................... 35
PDM Output ............................................................................... 35
Asynchronous Sample Rate Converters .................................. 36
Signal Levels ................................................................................ 36
Signal Processing ............................................................................ 37
Instructions ................................................................................. 37
Data Memory .............................................................................. 37
Parameters ................................................................................... 37
Control Port .................................................................................... 40
I2C Port ........................................................................................ 40
SPI Port ........................................................................................ 43
Self-Boot ...................................................................................... 44
Multipurpose Pins .......................................................................... 45
Push-Button Volume Controls ................................................. 45
Limiter Compression Enable .................................................... 45
Parameter Bank Switching ........................................................ 45
Mute ............................................................................................. 45
DSP Bypass Mode ...................................................................... 46
Serial Data Input/Output Ports .................................................... 47
Tristating Unused Channels...................................................... 47
Applications Information .............................................................. 50
Power Supply Bypass Capacitors.............................................. 50
Layout .......................................................................................... 50
Grounding ................................................................................... 50
Exposed Pad PCB Design ......................................................... 50
Register Summary .......................................................................... 51
Register Details ............................................................................... 53
Clock Control Register .............................................................. 53
PLL Denominator MSB Register.............................................. 54
PLL Denominator LSB Register ............................................... 54
PLL Numerator MSB Register .................................................. 54
PLL Numerator LSB Register.................................................... 55
PLL Integer Setting Register ..................................................... 55
PLL Lock Flag Register .............................................................. 56
CLKOUT Setting Selection Register........................................ 56
Regulator Control Register ....................................................... 57
Core Control Register................................................................ 58
Filter Engine and Limiter Control Register ............................ 59
DB Value Register 0 Read.......................................................... 60
DB Value Register 1 Read.......................................................... 60
DB Value Register 2 Read.......................................................... 61
Core Channel 0/Core Channel 1 Input Select Register......... 62
Core Channel 2/Core Channel 3 Input Select Register......... 63
DAC Input Select Register ........................................................ 64
PDM Modulator Input Select Register .................................... 65
Serial Data Output 0/Serial Data Output 1 Input Select
Register ........................................................................................ 66
Rev. C | Page 2 of 116
3Pages
Data Sheet
Parameter
Total Harmonic Distortion + Noise
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
With Flat 20 Hz to 20 kHz Filter
PGA Gain Variation
With −12 dB Setting
With +35.25 dB Setting
PGA Boost
PGA Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
Power Supply Rejection Ratio
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
0.90 × AVDD
Bias Current Source
Output Impedance
MICBIASx Isolation
Noise in the Signal Bandwidth3
DIGITAL-TO-ANALOG CONVERTERS
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC SINGLE-ENDED OUTPUT
Full-Scale Output Voltage
Mute Attenuation
Dynamic Range1
With A-Weighted Filter (RMS)
With Flat 20 Hz to 20 kHz Filter
Signal-to-Noise Ratio2
With A-Weighted Filter (RMS)
With Flat 20 Hz to 20 kHz Filter
Test Conditions/Comments
20 Hz to 20 kHz, −1 dBFS
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Standard deviation
Standard deviation
PGA_x_BOOST
PGA_MUTEx
Min
CM capacitor = 22 μF, 100 mV p-p at 1 kHz
MIC_ENx = 1
AVDD = 1.8 V, MIC_GAINx = 1
AVDD = 3.3 V, MIC_GAINx = 1
AVDD = 1.8 V, MIC_GAINx = 0
AVDD = 3.3 V, MIC_GAINx = 0
MIC_GAINx = 0
MIC_GAINx = 1
AVDD = 1.8 V, 20 Hz to 20 kHz
MIC_GAINx = 0
MIC_GAINx = 1
AVDD = 3.3 V, 20 Hz to 20 kHz
MIC_GAINx = 0
MIC_GAINx = 1
All DACs
Single-ended operation, HPOUTLP and
HPOUTRP pins
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD = 3.3 V, 0 dBFS
Line output mode, 20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Line output mode, 20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Rev. C | Page 5 of 116
Typ
−88
−90
96
102
94
99
0.05
0.15
10
−65
0.005
0
±0.2
83
63
ADAU1772
Max Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
dB
dB
dB
1.16
2.12
1.63
2.97
1
95
99
27
16
35
19
24
0.375
95
3
AVDD/3.4
0.53
1.5
0.97
2.74
−72
100
104
97
101
100
104
98
102
V
V
V
V
mA
Ω
dB
dB
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Bits
dB
dB
V rms
V rms
V p-p
V rms
V p-p
dB
dB
dB
dB
dB
dB
dB
dB
dB
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| ADAU1772 | Four ADC / Two DAC Low Power Codec | Analog Devices |
| ADAU1777 | Low Power Codec | Analog Devices |