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ADAU1372 の電気的特性と機能
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ADAU1372のメーカーはAnalog Devicesです、この部品の機能は「Low Power Codec」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 ADAU1372 |
| 部品説明 Low Power Codec |
| メーカ Analog Devices |
ロゴ |
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Data Sheet
Quad ADC, Dual DAC, Low Latency,
Low Power Codec
ADAU1372
FEATURES
APPLICATIONS
Low latency, 24-bit ADCs and DACs
102 dB SNR (through PGA and ADC with A-weighted filter)
107 dB dynamic range (through DAC and headphone with
A-weighted filter)
Serial port sample rates from 8 kHz to 192 kHz
4 single-ended analog inputs, configurable as microphone or
line inputs
Dual stereo digital microphone inputs
Stereo analog audio output, single-ended or differential,
configurable as either line output or headphone driver
PLL supporting any input clock rate from 8 MHz to 27 MHz
Full-duplex, asynchronous sample rate converters (ASRCs)
Power supplies
Analog and digital input/output of 1.8 V to 3.3 V
Low power (15.5 mW)
I2C and SPI control interfaces for flexibility
5 multipurpose pins supporting dual stereo digital
microphone inputs, mute, push-button volume controls
Handsets, headsets, and headphones
Bluetooth® handsets, headsets, and headphones
Personal navigation devices
Digital still and video cameras
GENERAL DESCRIPTION
The ADAU1372 is a codec with four inputs and two outputs, which
incorporates asynchronous sample rate converters. Optimized
for low latency and low power, the ADAU1372 is ideal for headsets,
handsets, and headphones. The ADAU1372 has built-in program-
mable gain amplifiers (PGAs); thus, with the addition of just a
few passive components and a crystal, the ADAU1372 provides
a solution for headset audio needs, microphone preamplifiers,
ADCs, DACs, headphone amplifiers, and serial ports for
connections to an external DSP.
Note that throughout this data sheet, multifunction pins, such as
SCL/SCLK, are referred to either by the entire pin name or by a
single function of the pin, for example, SCLK, when only that
function is relevant.
FUNCTIONAL BLOCK DIAGRAM
MICBIAS0
MICBIAS1
AIN0REF
AIN0
AIN1REF
AIN1
DMIC0_1/MP4
DMIC2_3/MP5
AIN2REF
AIN2
AIN3REF
AIN3
CM
MICROPHONE
BIAS GENERATORS
PGA
Σ-Δ ADC
PGA
Σ-Δ ADC
DIGITAL
MICROPHONE
INPUTS
PGA
Σ-Δ ADC
PGA
Σ-Δ ADC
ADAU1372
POWER
MANAGEMENT
LDO
REGULATOR
PLL
CLOCK
OSCILLATOR
DECIMATOR
DECIMATOR
INPUT/OUTPUT
SIGNAL ROUTING
Σ-Δ
DACs
DECIMATOR
DECIMATOR
BIDIRECTIONAL
ASRCS
SERIAL I/O PORT
Σ-Δ
DACs
I2C/SPI CONTROL
INTERFACE
ADC_SDATA1/CLKOUT/MP6
XTALI/MCLKIN
XTALO
HPOUTLP/LOUTLP
HPOUTLN/LOUTLN
HPOUTRP/LOUTRP
HPOUTRN/LOUTRN
Figure 1.
Rev. 0
Document Feedback
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
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Technical Support
www.analog.com
1 Page
ADAU1372
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Specifications..................................................................................... 4
Analog Performance Specifications ........................................... 4
Crystal Amplifier Specifications................................................. 7
Digital Input/Output Specifications........................................... 8
Power Supply Specifications........................................................ 8
Typical Power Consumption....................................................... 9
Digital Filters................................................................................. 9
Digital Timing Specifications ................................................... 10
Absolute Maximum Ratings.......................................................... 13
Thermal Resistance .................................................................... 13
ESD Caution................................................................................ 13
Pin Configuration and Function Descriptions........................... 14
Typical Performance Characteristics ........................................... 17
Theory of Operation ...................................................................... 24
System Clocking and Power-Up................................................... 25
Initialization ................................................................................ 25
Clock Initialization..................................................................... 25
PLL ............................................................................................... 25
Clock Output............................................................................... 26
Power Sequencing ...................................................................... 26
Signal Routing................................................................................. 27
Input Signal Paths........................................................................... 28
Analog Inputs.............................................................................. 28
Digital Microphone Input ......................................................... 29
Analog-to-Digital Converters................................................... 29
Output Signal Paths........................................................................ 30
Analog Outputs........................................................................... 30
Digital-to-Analog Converters................................................... 30
Asynchronous Sample Rate Converters .................................. 30
Control Port..................................................................................... 31
Burst Mode Communication.................................................... 31
I2C Port ........................................................................................ 31
SPI Port ........................................................................................ 34
Burst Mode Communication.................................................... 34
Multipurpose Pins .......................................................................... 35
Push-Button Volume Controls ................................................. 35
Mute ............................................................................................. 35
Talkthrough Mode ..................................................................... 35
Serial Data Input/Output Ports .................................................... 36
Serial Port Initialization ............................................................ 36
Tristating Unused Channels...................................................... 37
Applications Information .............................................................. 39
Power Supply Bypass Capacitors.............................................. 39
Layout .......................................................................................... 39
Grounding ................................................................................... 39
Exposed Pad PCB Design ......................................................... 39
System Block Diagram............................................................... 40
Register Summary: Low Latency Codec ..................................... 41
Register Details: Low Latency Codec .......................................... 43
Clock Control Register .............................................................. 43
PLL Denominator MSB Register.............................................. 44
PLL Denominator LSB Register ............................................... 44
PLL Numerator MSB Register .................................................. 44
PLL Numerator LSB Register.................................................... 44
PLL Integer Setting Register ..................................................... 45
PLL Lock Flag Register .............................................................. 46
CLKOUT Setting Selection Register........................................ 46
Regulator Control Register ....................................................... 47
DAC Input Select Register ........................................................ 47
Serial Data Output 0/Serial Data Output 1 Input Select
Register ........................................................................................ 48
Serial Data Output 2/Serial Data Output 3 Input Select
Register ........................................................................................ 49
Serial Data Output 4/Serial Data Output 5 Input Select
Register ........................................................................................ 50
Serial Data Output 6/Serial Data Output 7 Input Select
Register ........................................................................................ 51
ADC_SDATA0/ADC_SDATA1 Channel Select Register..... 53
Output ASRC0/Output ASRC1 Source Register.................... 53
Output ASRC2/Output ASRC3 Source Register.................... 54
Input ASRC Channel Select Register....................................... 56
ADC Control 0 Register ............................................................ 56
ADC Control 1 Register ............................................................ 57
ADC Control 2 Register ............................................................ 58
ADC Control 3 Register ............................................................ 59
ADC0 Volume Control Register .............................................. 60
Rev. 0 | Page 2 of 92
3Pages
Data Sheet
Parameter
THD + N
SNR2
With A-Weighted Filter (RMS)
With Flat 20 Hz to 20 kHz Filter
PGA Gain Variation
With −12 dB Setting
With +35.25 dB Setting
PGA Boost
PGA Mute Attenuation
Interchannel Gain Mismatch
Offset Error
Gain Error
Interchannel Isolation
PSRR
MICROPHONE BIAS
Bias Voltage
0.65 × AVDD
0.90 × AVDD
Bias Current Source
Output Impedance
MICBIASx Isolation
Noise in the Signal Bandwidth3
AVDD = 1.8 V
AVDD = 3.3 V
DIGITAL-TO-ANALOG CONVERTERS (DACs)
DAC Resolution
Digital Attenuation Step
Digital Attenuation Range
DAC SINGLE-ENDED OUTPUT
Full-Scale Output Voltage
Mute Attenuation
Line Output Mode
Dynamic Range1
With A-Weighted Filter (RMS)
With Flat 20 Hz to 20 kHz Filter
SNR2
With A-Weighted Filter (RMS)
Test Conditions/Comments
20 Hz to 20 kHz, −1 dBFS input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
Standard deviation
Standard deviation
PGA_x_BOOST
PGA_MUTEx
CM capacitor = 22 µF, 100 mV p-p at 1 kHz
MIC_ENx = 1
AVDD = 1.8 V, MIC_GAINx = 1
AVDD = 3.3 V, MIC_GAINx = 1
AVDD = 1.8 V, MIC_GAINx = 0
AVDD = 3.3 V, MIC_GAINx = 0
MIC_GAINx = 0
MIC_GAINx = 1
20 Hz to 20 kHz
MIC_GAINx = 0
MIC_GAINx = 1
MIC_GAINx = 0
MIC_GAINx = 1
All DACs
Single-ended operation, HPOUTLP/LOUTLP and
HPOUTRP/LOUTRP pins
Scales linearly with AVDD
AVDD = 1.8 V
AVDD = 1.8 V, 0 dBFS
AVDD = 3.3 V
AVDD = 3.3 V, 0 dBFS
20 Hz to 20 kHz, −60 dB input
AVDD = 1.8 V
AVDD = 3.3 V
AVDD = 1.8 V
AVDD = 3.3 V
20 Hz to 20 kHz
AVDD = 1.8 V
AVDD = 3.3 V
Rev. 0 | Page 5 of 92
Min Typ
−88
−90
96
102
94
99
0.05
0.15
10
−65
0.005
0
±0.2
83
63
ADAU1372
Max Unit
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
mV
dB
dB
dB
1.16 V
2.12 V
1.63 V
2.97 V
3 mA
1Ω
95 dB
99 dB
27
16
35
19
24
0.375
95
AVDD/3.4
0.53
1.50
0.97
2.74
−72
nV/√Hz
nV/√Hz
nV/√Hz
nV/√Hz
Bits
dB
dB
V rms
V rms
V p-p
V rms
V p-p
dB
100 dB
104 dB
97 dB
101 dB
100 dB
104 dB
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| ADAU1372 | Low Power Codec | Analog Devices |
| ADAU1373 | Low Power Codec | Analog Devices |