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ADP5041 の電気的特性と機能
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ADP5041のメーカーはAnalog Devicesです、この部品の機能は「Micro PMU」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 ADP5041 |
| 部品説明 Micro PMU |
| メーカ Analog Devices |
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Data Sheet
Micro PMU with 1.2 A Buck, Two 300 mA LDOs,
Supervisory, Watchdog, and Manual Reset
ADP5041
FEATURES
Input voltage range: 2.3 V to 5.5 V
One 1.2 A buck regulator
Two 300 mA LDOs
20-lead, 4 mm × 4 mm LFCSP package
Overcurrent and thermal protection
Soft start
Undervoltage lockout
Open-drain processor reset with externally adjustable
threshold monitoring
Guaranteed reset output valid to VAVIN = 1 V
Manual reset input
Watchdog refresh input
Buck key specifications
Output voltage range: 0.8 V to 3.8 V
Current mode topology for excellent transient response
3 MHz operating frequency
Peak efficiency up to 96%
Uses tiny multilayer inductors and capacitors
Mode pin selects forced PWM or auto PWM/PSM mode
100% duty cycle low dropout mode
LDOs key specifications
Output voltage range: 0.8 V to 5.2 V
Low input supply voltage from 1.7 V to 5.5 V
Stable with 2.2 μF ceramic output capacitors
High PSRR
Low output noise
Low dropout voltage
−40°C to +125°C junction temperature range
GENERAL DESCRIPTION
The ADP5041 combines one high performance buck regulator
and two low dropout regulators (LDO) in a small 20-lead
LFCSP to meet demanding performance and board space
requirements.
The high switching frequency of the buck regulator enables
use of tiny multilayer external components and minimizes
board space.
When the MODE pin is set to logic high, the buck regulator
operates in forced PWM mode. When the MODE pin is set to
logic low, the buck regulator operates in PWM mode when the
load is around the nominal value. When the load current falls
below a predefined threshold, the regulator operates in power
save mode (PSM), improving the light load efficiency. The low
quiescent current, low dropout voltage, and wide input voltage
FUNCTIONAL BLOCK DIAGRAM
RFILT = 30Ω
AVIN
VIN1
=
2.3V TO
5.5V
VIN2 = 1.7V
TO 5.5V
C1
4.7µF
ON
OFF
VBIAS
VIN1
BUCK
EN_BK
EN1
C2
1µF
ON
OFF
VIN2
EN2
MR
LDO1
(DIGITAL)
EN_LDO1
VBIAS
SUPERVISOR
ON
OFF
EN3
VIN3 = 1.7V
TO 5.5V
VIN3
C3
1µF
EN_LDO2
LDO2
(ANALOG)
AGND
VOUT1
SW
FB1
R2
PGND
L1
1µH
R1
VOUT1 AT
1.2A
C6
10µF
MODE
VOUT2
FB2
R4
FPWM
PSM/PWM
R3
C5
2.2µF
VOUT2 AT
300mA
nRSTO
WDI
VTHR
R4
µP
R5
VOUT3
FB3
R3
R7
VOUT3 AT
300mA
C6
2.2µF
Figure 1.
range of the ADP5041 LDOs extend the battery life of portable
devices. The ADP5041 LDOs maintain a power supply rejection
greater than 60 dB for frequencies as high as 10 kHz while
operating with a low headroom voltage.
Each regulator in the ADP5041 is activated by a high level on
the respective enable pin. The output voltages of the regulators
and the reset threshold are programmed through external resistor
dividers to address a variety of applications. The ADP5041
contains supervisory circuits that monitor power supply voltage
levels and code execution integrity in microprocessor-based
systems. They also provide power-on reset signals. An on-chip
watchdog timer can reset the microprocessor if it fails to strobe
within a preset timeout period.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
1 Page
ADP5041
TABLE OF CONTENTS
Features .............................................................................................. 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
General Specifications ................................................................. 3
Supervisory Specifications .......................................................... 3
Buck Specifications....................................................................... 4
LDO1, LDO2 Specifications ....................................................... 5
Input and Output Capacitor, Recommended Specifications.. 6
Absolute Maximum Ratings............................................................ 7
Thermal Resistance ...................................................................... 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ............................................. 9
Theory of Operation ...................................................................... 26
Power Management Unit........................................................... 26
REVISION HISTORY
12/11—Revision 0: Initial Version
Data Sheet
Buck Section................................................................................ 27
LDO Section ............................................................................... 28
Supervisory Section ................................................................... 28
Applications Information .............................................................. 31
Buck External Component Selection....................................... 31
LDO External Component Selection ...................................... 32
Output Capacitor........................................................................ 32
Supervisory Section ................................................................... 33
Power Dissipation/Thermal Considerations ............................. 34
Application Diagram ................................................................. 36
PCB Layout Guidelines.................................................................. 37
Suggested Layout ........................................................................ 37
Bill of Materials........................................................................... 38
Factory Programmable Options ................................................... 39
Outline Dimensions ....................................................................... 40
Ordering Guide .......................................................................... 40
Rev. 0 | Page 2 of 40
3Pages
Data Sheet
ADP5041
LDO1, LDO2 SPECIFICATIONS
VIN2, VIN3 = (VOUT2,VOUT3 + 0.5 V) or 1.7 V (whichever is greater) to 5.5 V; AVIN, VIN1 ≥ VIN2, VIN3; CIN = 1 µF, COUT = 2.2 µF;
TJ= −40°C to +125°C for minimum/maximum specifications and TA = 25°C for typical specifications, unless otherwise noted.1
Table 4.
Parameter
INPUT VOLTAGE RANGE
OPERATING SUPPLY CURRENT
Bias Current per LDO2
Symbol
VIN2, VIN3
IVIN2BIAS/IVIN3BIAS
Conditions
TJ = −40°C to +125°C
IOUT3 = IOUT4 = 0 µA
IOUT2 = IOUT3 = 10 mA
IOUT2 = IOUT3 = 300 mA
Min
Typ Max
Unit
1.7 5.5 V
10 30
60 100
165 245
µA
µA
µA
Total System Input Current
LDO1 or LDO2 Only
LDO1 and LDO2 Only
OUTPUT VOLTAGE ACCURACY
REFERENCE VOLTAGE
REGULATION
Line Regulation
Load Regulation3
DROPOUT VOLTAGE4
ACTIVE PULL-DOWN
CURRENT-LIMIT THRESHOLD5
OUTPUT NOISE
POWER SUPPLY REJECTION
RATIO
IIN
VOUT2, VOUT3
VFB2,VFB3
Includes all current into AVIN, VIN1, VIN2, and
VIN3
IOUT2 = IOUT3 = 0 µA, all other channels disabled
IOUT2 = IOUT3 = 0 µA, buck disabled
100 µA < IOUT2 < 300 mA, 100 µA < IOUT3 < 300 mA
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
VIN3 = (VOUT3 + 0.5 V) to 5.5 V
(ΔVOUT2/VOUT2)/ΔVIN2
(ΔVOUT3/VOUT3)/ΔVIN3
(ΔVOUT2/VOUT2)/ΔIOUT2
(ΔVOUT3/VOUT3)/ΔIOUT3
VDROPOUT
RPDLDO
ILIMIT
OUTLDO2NOISE
OUTLDO1NOISE
PSRR
VIN2 = (VOUT2 + 0.5 V) to 5.5 V
VIN3 = (VOUT3 + 0.5 V) to 5.5 V
IOUT2 = IOUT3 = 1 mA
IOUT2 = IOUT3 = 1 mA to 300 mA
VOUT2 = VOUT3 = 5.0 V, IOUT2 = IOUT3 = 300 mA
VOUT2 = VOUT3 = 3.3 V, IOUT2 = IOUT3 = 300 mA
VOUT2 = VOUT3 = 2.5 V, IOUT2 = IOUT3 = 300 mA
VOUT2 = VOUT3 = 1.8 V, IOUT2 = IOUT3 = 300 mA
EN2/EN3 = 0 V
TJ = −40°C to +125°C
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 3.3 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 2.8 V
10 Hz to 100 kHz, VIN3 = 5 V, VOUT3 = 1.5 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 3.3 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 2.8 V
10 Hz to 100 kHz, VIN2 = 5 V, VOUT2 = 1.5 V
1 kHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
100 kHz, VIN2,VIN3 = 3.3 V, VOUT2,VOUT3 = 2.8 V,
IOUT = 100 mA
1 MHz, VIN2, VIN3 = 3.3 V, VOUT2, VOUT3 = 2.8 V,
IOUT = 100 mA
−3
0.485
−0.03
335
53
74
+3
µA
µA
%
0.500
0.515
+0.03
V
%/ V
0.002 0.0075 %/mA
72
86 140
107
180
600
470
123
110
59
140
129
66
66
57
60
mV
mV
mV
mV
Ω
mA
µV rms
µV rms
µV rms
µV rms
µV rms
µV rms
dB
dB
dB
1 All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
2 This is the input current into VIN2 and VIN3 that is not delivered to the output load.
3 Based on an end-point calculation using 1 mA and 300 mA loads.
4 Dropout voltage is defined as the input-to-output voltage differential when the input voltage is set to the nominal output voltage. This applies only to output voltages
above 1.7 V.
5 Current-limit threshold is defined as the current at which the output voltage drops to 90% of the specified typical value. For example, the current limit for a 3.0 V
output voltage is defined as the current that causes the output voltage to drop to 90% of 3.0 V, or 2.7 V.
Rev. 0 | Page 5 of 40
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| ADP5040 | Micro PMU | Analog Devices |
| ADP5041 | Micro PMU | Analog Devices |
| ADP5042 | Micro PMU | Analog Devices |
| ADP5043 | Micro PMU | Analog Devices |