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DM9331A の電気的特性と機能
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DM9331AのメーカーはDAVICOMです、この部品の機能は「100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9331A |
| 部品説明 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9331Aダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
1. General Description
The DM9331A is a physical-layer, single-chip, low
power transceiver for media converter application. On
the media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5)
for 100BASE-TX Fast Ethernet, and it also provides
PECL interface to connect the external fiber optical
transceiver. Through the Media Converter Interface
(MCI), the DM9331A connects to another DM9331A
for the twisted pair to the fiber media converter, or
fiber to fiber repeater.
The DM9331A uses a low-power and
high-performance CMOS process. It contains the
entire physical layer functions of 100BASE-TX as
defined by IEEE802.3u, including the Physical
Coding Sublayer (PCS), Physical Medium
Attachment (PMA), Twisted Pair Physical Medium
Dependent Sublayer (TP-PMD) and a PECL
compliant interface for a fiber optical module,
compliant with ANSI X3.166. The DM9331A provides
a strong support for the auto-negotiation function,
utilizing automatic selection of full or half-duplex
mode. Furthermore, due to the built-in wave-shaping
filter, the DM9331A needs no external filter to
transport signals to the media on the 100base-TX
Ethernet operation.
2. Block Diagram
100Base-FX
PECL
Interface
100Base-TX
Transceiver
Clock
Circuit
Block
100Base-
TX
PCS
Media
Converter
Interface
Auto-Negotiation
TX/RX Module
Biasing/
Power
Block
MII
Register
LED Driver
MII
Management
Control
Preliminary
Version: DM9331A-DS-P02
October 7, 2008
1
1 Page
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
10.7 Power Plane Partitioning ................................ 36
10.8 Media Converter Interface.............................. 37
10.9 Link Fault Propagation Application................. 38
10.10 Auto-loopback Diagnostic............................. 39
10.11 Media Converter or Repeater
Application…….40
10.12 Link Fault Propagation LED Display ....... ….41
10.13 Magnetics Selection Guide .......................... 42
11. Package Information ........................................ 43
12. Ordering Information ........................................ 44
Preliminary
Version: DM9331A-DS-P02
October 20, 2008
3
3Pages
DM9331A
100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip
5. Pin Description
I : Input, O : Output, LI : Latch input when power-up/reset, Z : Tri-State output, U : Pulled up
D : Pulled down
5.1 Media Converter Interface, 18 pins
Pin No.
14
17
18
20,19
21
22
24
25
26
27
29,28
Pin Name
TPFAULT
LNKFAULT#
LNKFAULTEN
TXD [0:1]
TXEN
TXCLK
MDC
MDIO
FXFAULT/
TPSET1
TPSET0
RXD [0:1]
I/O Description
O Twisted Pair Fault
0 = Twisted pair link fault
1 = Twisted pair normal work
I Link Fault Propagation
0 = Link fault propagation is active
1 = normal operation
I Link Fault Propagation Enable
0 = Link fault propagation disable
1 = Link fault propagation enable
I Transmit Data
2-bit data inputs (synchronous to the 50MHz OSCIN)
I Transmit Enable
Active high indicates the presence of valid data on the TXD [0:1] for
100Mbps mode
O Transmit Clock
25MHz transmit clock
I Management Data Clock
Synchronous clock for the MDIO management data. This clock is
provided by management entity, and it is up to 2.5MHz
I/O Management Data I/O
Bi-directional management data that may be provided by the station
management entity or the PHY
O, Fiber Fault
Z, 0 = Fiber link fault; Fiber receive far end fault package or fiber
LI disconnect
(D) 1 = Fiber normal work
TPSET1 (reset latch input)
0 = Fiber mode; default pull low
1 = Twisted pair mode; need 10kΩ resistor to pull high
Z, Twisted Pair set (reset latch input)
LI 0 = Fiber mode; default pull low
(D) 1 = Twisted pair mode; need 10kΩ resistor to pull high
O, Receive Data Output
Z, 2-bit data outputs (synchronous to the 50MHz OSCIN)
LI Chip PHY-address of Management Register (reset latch input)
(D) RXD [0:1]
FX Mode:
TP Mode:
0,0 PHY-address =
0X00
0X0C
0,1 PHY-address =
0X01
0X0D
1,0 PHY-address =
0X02
0X0E
1,1 PHY-address =
0X03
0X0F
0 = Defaults
1 = Needs 10kΩ register to pull high
6 Preliminary
Version: DM9331A-DS-P02
October 20, 2008
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| DM9331A | 100 Mbps Twisted Pair/Fiber Ethernet Media Converter Chip | DAVICOM |