|
DM9302 の電気的特性と機能
|
DM9302のメーカーはDAVICOMです、この部品の機能は「10/100Mbps Ethernet Fiber/Twisted Pair Media Converter」です。 |
|
|
製品の詳細 ( Datasheet PDF )
| 部品番号 DM9302 |
| 部品説明 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9302ダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
No Preview Available ! |
DAVICOM Semiconductor, Inc.
DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media
Converter with Local bus
DATA SHEET
Preliminary
Version: DM9302-DS-P01
July 30, 2009
1 Page
DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
6.5 RX Status Register (06H) .............................................................................................................................. 18
6.6 Receive Overflow Counter Register (07H) .................................................................................................. 18
6.7 Flow Control Register (0AH)......................................................................................................................... 18
6.8 EEPROM & PHY Control Register (0BH) ..................................................................................................... 18
6.9 EEPROM & PHY Address Register (0CH) ................................................................................................... 19
6.10 EEPROM & PHY Data Registers (0DH~0EH)............................................................................................. 19
6.11 Link Change Control Register (0FH) ......................................................................................................... 19
6.12 Processor Port Physical Address Registers (10H~15H) ......................................................................... 19
6.13 Processor Port Multicast Address Registers (16H~1DH)........................................................................ 19
6.14 RX Packet Length Low Register ( 20H ) .................................................................................................... 20
6.15 RX Packet Length High Register ( 21H ) ................................................................................................... 20
6.16 RX Additional Status Register ( 26H ) ....................................................................................................... 20
6.17 RX Additional Control Register ( 27H )...................................................................................................... 20
6.18 Vendor ID Registers (28H~29H) ................................................................................................................. 20
6.19 Chip Revision Register (2CH) .................................................................................................................... 20
6.20 Transmit Check Sum Control Register (31H) ........................................................................................... 20
6.21 Receive Check Sum Control Status Register (32H)................................................................................. 21
6.22 uP Data Bus driving capability Register (38H) ......................................................................................... 21
6.23 IRQ Pin Control Register (39H) .................................................................................................................. 21
6.24 TX/RX Memory Size Control Register (3FH) ............................................................................................. 22
Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
3
3Pages
DM9302
10/100Mbps Ethernet Fiber/Twisted Pair Media Converter with Local bus
8.8 DAVICOM Specified Configuration Register (DSCR) – 10H ...................................................................... 43
8.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H ................................................ 44
8.10 10BASE-T Configuration/Status (10BTCSR) – 12H.................................................................................. 45
8.11 Power Down Control Register (PWDOR) – 13H........................................................................................ 45
8.12 (Specified config) Register – 14H .............................................................................................................. 46
8.13 DAVICOM Specified Receive Error Counter Register (RECR) – 16H ..................................................... 47
8.14 DAVICOM Specified Disconnect Counter Register (DISCR) – 17H ........................................................ 47
8.15 Power Saving Control Register (PSCR) – 1DH ......................................................................................... 47
9. FUNCTIONAL DESCRIPTION....................................................................................... 48
9.1 Processor bus and memory management function: ................................................................................. 48
9.1.1 Processor Interface .................................................................................................................................. 48
9.1.2 Direct Memory Access Control................................................................................................................. 48
9.1.3 Packet Transmission................................................................................................................................ 48
9.1.4 Packet Reception ..................................................................................................................................... 48
9.2 Switch function:............................................................................................................................................. 49
9.2.1 Address Learning ..................................................................................................................................... 49
9.2.2 Address Aging .......................................................................................................................................... 49
9.2.3 Packet Forwarding ................................................................................................................................... 49
9.2.4 Inter-Packet Gap (IPG) ............................................................................................................................ 49
9.2.5 Back-off Algorithm.................................................................................................................................... 49
9.2.6 Late Collision............................................................................................................................................ 49
9.2.7 Half Duplex Flow Control ......................................................................................................................... 49
9.2.8 Full Duplex Flow Control .......................................................................................................................... 49
9.2.9 Partition Mode .......................................................................................................................................... 49
9.2.10 Broadcast Storm Filtering....................................................................................................................... 50
9.2.11 Bandwidth Control.................................................................................................................................. 50
9.2.12 Port Monitoring Support ......................................................................................................................... 50
6 Preliminary datasheet
DM9302-15-DS-P01
July 30, 2009
6 Page
合計 : 30 ページ |
| PDF ダウンロード [ DM9302 データシート.PDF ] |
|
データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
|
|
| 部品番号 | 部品説明 | メーカ |
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter | DAVICOM |
| DM9301FP | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |  Davicom |
| DM9302 | 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter | DAVICOM |
| DM9308 | Dual 4-Bit Latch |  National |