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DM9801A の電気的特性と機能
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DM9801AのメーカーはDavicomです、この部品の機能は「1M Home Phoneline Network Physical Layer Single Chip Transceiver」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9801A |
| 部品説明 1M Home Phoneline Network Physical Layer Single Chip Transceiver |
| メーカ Davicom |
ロゴ |
このページの下部にプレビューとDM9801Aダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
General Description
The DM9801A is a physical-layer, single-chip, low-power
transceiver for 1M Home Phoneline Network applications.
On the media side, it provides an interface to a Home
Phoneline wiring system. The reconciliation layer interfaces
to the DM9801A either through an IEEE802.3u subset
Media Independent Interface (MII) or a pseudo-standard
General Purpose Serial Interface (GPSI). A management
interface is provided by MDIO/MDC when operating in MII
mode, or a Serial Peripheral Interface bus when operating in
GPSI mode.
The DM9801A uses a low-power and high-performance
CMOS process. It contains the entire physical layer
functions of 1M as defined by Home Phoneline Network
Alliance, Rev. 1.1, including the Physical Coding Sublayer,
(RLL25) Encoder/Decoder (ENC/DEC), 4-wire HN Driver
circuit and receiver analog front end (AFE).
Patent-Pending Circuitry Includes:
Enhanced 4-wire Home Network transceiver circuit.
Compatible with HomePNA 1M PHY specification version
1.1 and HomePNA certification document version 1.0
Block Diagram
GPSI - MII
Transmit
GPSI - MII
Receive
Muxed
GPSI
or Mii
Interface
RLL25
Encoder
Master
PHY
Controller
Transmit
Timing
Generator
HN
Secondary
Driver
HNB+/-
HN
Primary
Driver
HNA+/-
Interface
Select
RLL25
Decoder
Receiever
and
Digital PLL
Receiver
AFE
Final
Version: DM9801A-DS-F01
May 30, 2001
1
1 Page
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Pin Configuration: DM9801A, 100-pin LQFP
NC
NC
NC
DVCC
NC
INT#
LNKSTA
PHYAD1
PHYAD2
PHYAD3
COLLED#
RXLED#(LNKLED#)
TXLED#(ACTLED#)
DGND
NC
NC
NC
NC
AVCC
NC
BGREF
BGGND
NC
NC
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75 NC
74 NC
73 NC
72 DVCC
71 DVCC
70 NC
69 NC
68 PHYAD0
67 MDIO(SCS#)
66 MDC(BP0)
65 TRIDRV
64 RESET#
63 CONFIG0
62 CONFIG1
61 INTFSEL
60 CMDENA
59 SPDSEL
58 PWSEL
57 FWENA
56 NC
55 DGND
54 NC
53 TSTMODE
52 NC
51 NC
Final
Version: DM9801A-DS-F01
May 30, 2001
3
3Pages
DM9801A
1M Home Phoneline Network Physical Layer Single Chip Transceiver
Pin Description (Continued)
PHY Address Interface:
PHYAD[4:0] provides up to 32 unique PHY address. An address selection of all zeros (00000) will result in a
PHY isolation condition. See the isolate bit description in the BMCR, address 00.
68 PHYADSEL I/O,Z MII Serial Management PHY Address Select (MII Mode, INTFSEL = 0):
(PHYAD0)
PHYADSEL is an input signal that selects one of two PHY addresses within
Or
SCLK
the 32 address range for the DM9801A MII management interface when
both CONFIG1 and CONFIG0 are not set to 1.
0 = 0x01 address
1 = 0x1F address
PHY Address 0 (MII Mode, i.e. INTFSEL = 0 or GM_MODE, i.e.
INTFSEL=1, CONFIG1=1, and CONFIG0=1):
PHY address bit 0 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1.
Serial Interface Clock (Standard GPSI Mode, INTFSEL = 1):
SCLK is a bi-directional clock signal used to synchronize SI, SO and SCS#
to and from the DM9801A SPI bus.
8 PHYAD1 I/O, PHY Address 1 (MII Mode, INTFSEL = 0, or GM_MODE, i.e. INTFSEL=1,
Z CONFIG1=1, and CONFIG0=1):
PHY address bit 1 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
9 PHYAD2 I/O, PHY Address 2 (MII Mode, INTFSEL = 0, or GM_MODE, i.e. INTFSEL=1,
Z CONFIG1=1, and CONFIG0=1):
PHY address bit 2 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
10 PHYAD3 I/O, PHY Address 3 (MII Mode, INTFSEL = 0), or GM_MODE, i.e.
Z INTFSEL=1, CONFIG1=1, and CONFIG0=1:
PHY address bit 3 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
47 PHYAD4 I/O, PHY Address 4 (MII Mode, INTFSEL = 0), or GM_MODE, i.e.
Z INTFSEL=1, CONFIG1=1, and CONFIG0=1:
PHY address bit 4 for multiple PHY address applications. Both CONFIG1
and CONFIG0 must be set to 1. Leave unconnected when both CONFIG1
and CONFIG0 are not 1.
Pin Description (Continued)
Pin No. Pin Name I/O
Description
Configuration and Control Interface:
64
RESET#
I Reset:
Active Low input that initializes the DM9801A. Should remain low for 10ms
after VCC has stabilized at 3.3Vdc (nominal) before it transitions to high.
63
CONFIG0
I Configuration Select 1:0:
62 CONFIG1
These input pins select the DM9801A configuration from a reset condition.
6 Final
Version: DM9801A-DS-F01
May 30, 2001
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| DM9801A | 1M Home Phoneline Network Physical Layer Single Chip Transceiver | Davicom |