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DM9161BI の電気的特性と機能
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DM9161BIのメーカーはDAVICOMです、この部品の機能は「Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9161BI |
| 部品説明 Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9161BIダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DAVICOM Semiconductor, Inc.
DM9161BI
Industrial-grade 10/100 Mbps Fast Ethernet
Physical Layer Single Chip Transceiver
DATA SHEET
Preliminary
Version: DM9161BI-DS-P01
July 16, 2008
1 Preliminary
Version: DM9161BI-DS-P01
July 16, 2008
1 Page
DM9161BI
Industry-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
1. General Description
The DM9161BI is a Industrial-grade physical layer,
single-chip, and low power transceiver for
100BASE-TX and 10BASE-T operations. On the
media side, it provides a direct interface either to
Unshielded Twisted Pair Category 5 Cable (UTP5) for
100BASE-TX Fast Ethernet, or UTP5/UTP3 Cable for
10BASE-T Ethernet. Through the Media Independent
Interface (MII), the DM9161BI connects to the Medium
Access Control (MAC) layer, ensuring a high inter
operability from different vendors.
The DM9161BI uses a low power and high
performance advanced CMOS process. It contains the
Entire physical layer functions of 100BASE-TX as
defined by IEEE802.3u, including the Physical Coding
Sub layer (PCS), Physical Medium Attachment (PMA),
Twisted Pair Physical Medium Dependent Sub layer
(TP-PMD),
10BASE-TX
Encoder/Decoder
(ENC/DEC), and Twisted Pair Media Access Unit
(TPMAU). The DM9161BI provides a strong support
for the auto-negotiation function, utilizing automatic
media speed and protocol selection. Furthermore, due
to the built-in wave shaping filter, the DM9161BI needs
no external filter to transport signals to the media in
100BASE-TX or 10BASE-T Ethernet operation.
2. Features
Fully comply with IEEE 802.3 / IEEE 802.3u 10Base-T/
100Base-TX, ANSI X3T12 TP-PMD 1995 standard
Support HP MDI/MDI-X auto crossover function
(HP Auto-MDIX)
Support Auto-Negotiation function, compliant with IEEE
802.3u
Fully integrated Physical layer transceiver On-chip
filtering with direct interface to magnetic transformer
Selectable repeater or node mode
Selectable MII or RMII (Reduced MII) mode for
100Base-TX and 10Base-TX. Selectable MII or GPSI
(7-Wired) mode for 10Base-T
Selectable full-duplex or half-duplex operation
MII management interface with mask able interrupt
output capability
Provide Loopback mode for easy system
diagnostics
LED status outputs indicate Link/ Activity, Speed10/100
and Full-duplex/Collision. Support Dual-LED optional
control
Single low power Supply of 3.3V with an advanced
CMOS technology
Very Low Power consumption modes:
● Power Reduced mode (cable detection)
● Power Down mode
● Selectable TX drivers for 1:1 or 1.25:1 transformers
for additional power reduction. 1: 1 transformers only
when HP Auto-MDIX Enable.
Compatible with 3.3V and 5.0V tolerant I/Os
Pin to pin Compatible with DM9161A.
DSP architecture PHY Transceiver.
Supports Industrial-grade: -40°C.~ +85'°C,
48-pin LQFP 0.18um process
Preliminary
Version: DM9161BI-12-DS-P01
July 16, 2008
2
3Pages
5. Pin Description
DM9161BI
Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver
I: Input, O: Output, LI: Latch input when power-up/reset, Z: Tri-State output, U: Pulled high D: Pulled low
5.1 Normal MII Interface, 21 pins
Pin No.
Pin Name I/O
Description
16 TXER/TXD [4] I Transmit Error/The Fifth TXD Data Bit
In 100Mbps mode, when the signal indicates active high and TXEN is
active, the HALT symbol substitutes the actual data nibble.
In 10Mbps, the input is ignored
In bypass mode (bypass BP4B5B), TXER becomes the TXD [4] pin, the
fifth TXD data bit of the 5B symbol
20,19,18,17
TXD [0:3]
I Transmit Data
4-bit nibble data inputs (synchronous to the TXCLK) when in 10/100Mbps
nibble mode.
In 10Mbps GPSI (7-Wired) mode, the TXD [0] pin is used as the serial
data input pin, and TXD [1:3] are ignored.
21 TXEN
22 TXCLK/
ISOLATE
24 MDC
25 MDIO
29,28,27,26
RXD[0:3]
/PHYAD[0:3]
32 MDINTR
I Transmit Enable
Active high indicates the presence of valid nibble data on the TXD [0:3] for
both 100Mbps and 10Mbps nibble modes.
In 10Mbps GPSI (7-Wired) mode, active high indicates the presence of
valid 10Mbps data on TXD [0].
O, Transmit Clock
Z, The transmitting clock provides the timing reference for the transfer of the
LI TXEN, TXD, and TXER. TXCLK is provided by the PHY
(D) 25MHz in 100Mbps nibble mode, 2.5MHz in 10Mbps nibble mode, 10MHz
in 10Mbps GPSI (7-Wired) mode
ISOLATE Setting: (When power up reset, latch input)
0: Reg 0.10 will be initialized to “0”. (Ref.to 8.1 Basic Control Register)
1: Reg 0.10 will be initialized to “1”.
I Management Data Clock
Synchronous clock for the MDIO management data. This clock is
provided by management entity, and it is up to 2.5MHz
I/O Management Data I/O
Bi-directional management data which may be provided by the station
management entity or the PHY
O, Receive Data Output
Z, 4-bit nibble data outputs (synchronous to RXCLK) when in 10/100Mbps
LI MII mode
(D) In 10Mbps GPSI (7-Wired) mode, the RXD [0] pin is used as the serial
data output pin, and the RXD [1:3] are ignored
PHY address [0:3] (power up reset latch input)
PHY address sensing input pins
IO, Status Interrupt Output:
LI Whenever there is a status change (link, speed, duplex depend on
(D) interrupt register [21] )
The interrupt output assert low when pull up.
Asserted high when pull down.
Preliminary
Version: DM9161BI-12-DS-P01
July 16, 2008
6
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| DM9161B | 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver | DAVICOM |
| DM9161BI | Industrial-grade 10/100 Mbps Fast Ethernet Physical Layer Single Chip Transceiver | DAVICOM |