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DM9102H の電気的特性と機能
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DM9102HのメーカーはDAVICOMです、この部品の機能は「Single Chip Fast Ethernet NIC Controller」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9102H |
| 部品説明 Single Chip Fast Ethernet NIC Controller |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9102Hダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DM9102H
Single Chip Fast Ethernet NIC Controller
DAVICOM Semiconductor, Inc.
DM9102H
Single Chip Fast Ethernet
NIC Controller
DATA SHEET
Final
Version: DM9102H-12-DS-F01
February 15, 2008
Final
Version: DM9102H-DS-F01
February 15, 2008
1 Page
DM9102H
Single Chip Fast Ethernet NIC Controller
6.2.12 Sample Frame Access Register (CR13) ................................................................................................... 29
6.2.13 Sample Frame Data Register (CR14)....................................................................................................... 29
6.2.14 Watchdog and Jabber Timer Register (CR15)................................................................................... 29
6.3 PHY Management Register Set .................................................................................................................. 30
6.3.1 Basic Mode Control Register (BMCR) – 0........................................................................................... 31
6.3.2 Basic Mode Status Register (BMSR) – 1............................................................................................. 32
6.3.3 PHY Identifier Register #1 (PHYIDR1) – 2 .......................................................................................... 33
6.3.4 PHY Identifier Register #2 (PHYIDR2) - 3 ........................................................................................... 33
6.3.5 Auto-negotiation Advertisement Register (ANAR) – 4 ......................................................................... 33
6.3.6 Auto-negotiation Link Partner Ability Register (ANLPAR) – 5.............................................................. 35
6.3.7 Auto-negotiation Expansion Register (ANER) – 6 ............................................................................... 36
6.3.8 DAVICOM Specified Configuration Register (DSCR) – 10H ............................................................... 36
6.3.9 DAVICOM Specified Configuration and Status Register (DSCSR) – 11H ........................................... 37
6.3.10 10BASE-T Configuration/Status (10BTCSRCSR) – 12H .................................................................. 38
6.3.11 Power down Control Register (PWDOR) – 13H ................................................................................ 38
6.3.12 (Specified config) Register – 20......................................................................................................... 39
6.3.13 Power Saving Control Register (PSCR) – 1DH................................................................................. 40
7. Functional Description.................................................................................................... 41
7.1 System Buffer Management........................................................................................................................ 41
7.1.1 Overview .............................................................................................................................................. 41
7.1.2 Data Structure and Descriptor List....................................................................................................... 41
7.1.3 Buffer Management -- Chain Structure Method................................................................................... 41
7.1.4 Descriptor List: Buffer Descriptor Format ............................................................................................ 42
7.1.5 Setup Frame ........................................................................................................................................ 46
7.2 Initialization Procedure................................................................................................................................ 48
7.2.1 Data Buffer Processing Algorithm........................................................................................................ 48
7.2.2 Receive Data Buffer Processing.......................................................................................................... 48
7.2.3 Transmit Data Buffer Processing ......................................................................................................... 49
7.3 Network Function ........................................................................................................................................ 50
7.3.1 Overview .............................................................................................................................................. 50
7.3.2 Receive Process and State Machine ................................................................................................... 50
7.3.3 Transmit Process and State Machine .................................................................................................. 50
7.3.4 Physical Layer Overview ..................................................................................................................... 50
7.4 Serial Management Interface ...................................................................................................................... 51
7.4.1 Management Interface - Read Frame Structure .................................................................................. 51
7.4.2 Management Interface - Write Frame Structure .................................................................................. 51
7.5 Power Management .................................................................................................................................... 52
7.5.1 Overview .............................................................................................................................................. 52
7.5.2 PCI Function Power Management States............................................................................................ 52
7.5.3 The Power Management Operation..................................................................................................... 52
7.6 Sample Frame Programming Guide: .......................................................................................................... 54
7.7 EEPROM Overview..................................................................................................................................... 55
7.7.1 Subsystem ID Block............................................................................................................................. 55
7.7.2Vendor ID .............................................................................................................................................. 55
7.7.3 Word Offset (04): Auto_ Load_ Control ............................................................................................... 55
7.7.4 Word Offset (04): New_ Capabilities_ Enable ..................................................................................... 55
7.7.5 Word Offset (07): PMC ........................................................................................................................ 55
7.7.6 Word Offset (07): Control..................................................................................................................... 55
Final
Version: DM9102H-12-DS-F01
February 15, 2008
3Pages
DM9102H
Single Chip Fast Ethernet NIC Controller
3. Features
Integrated Fast Ethernet MAC, Physical Layer and
Transceiver in one chip.
Comply with PCI specification 2.2.
PCI clock up to 66MHz.
PCI bus master architecture.
PCI bus burst mode data transfer.
Two large independent transmission and receipt of
FIFO
Support transmit threshold under-run re-try mode
Up to 256K bytes Boot EPROM or Flash interface.
EEPROM 93C46 interface automatically supports node
ID load and configuration information.
Comply with IEEE 802.3u 100Base-TX and 802.3
10Base-T.
Comply with IEEE 802.3u auto-negotiation protocol for
automatic link type selection.
Support IEEE 802.3x Full Duplex Flow Control
VLAN frame length support.
IP/TCP/UDP checksum generation and checking
Comply with ACPI and PCI Bus Power Management.
Support the MII (Media Independent Interface) for an
external PHY
Support Wake-On-LAN function and remote wake-up
(Magic packet, Link Change and Microsoft® wake-up
frame).
Support 4 Wake-On-LAN (WOL) signals (active high
pulse, active low pulse, and active high, active low.)
High performance 100Mbps clock generator and data
recovery circuit.
Digital clock recovery circuit, using advanced digital
algorithm to reduce jitter.
Provides Loopback mode for easy system diagnostics.
Support auto-MDIX
+1.8/3.3V Power supply with +5V tolerant I/O.
128 pin LQFP with CMOS process.
Final
Version: DM9102H-12-DS-F01
February 15, 2008
1
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| DM9102A | Single Chip Fast Ethernet NIC controller | DAVICOM |
| DM9102D | SINGLE CHIP FAST ETHEMET NIC CONTROLLER | DAVICOM |
| DM9102H | Single Chip Fast Ethernet NIC Controller | DAVICOM |