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DM9010BI の電気的特性と機能
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DM9010BIのメーカーはDAVICOMです、この部品の機能は「Industrial-temperature 10/100 MbpsSingle Chip Ethernet Controller」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9010BI |
| 部品説明 Industrial-temperature 10/100 MbpsSingle Chip Ethernet Controller |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9010BIダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9010BI
Industrial-temperature 10/100 Mbps Single Chip
Ethernet Controller
With General Processor Interface
DATA SHEET
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
Preliminary
Version: DM9010BI-DS-P01
January 12, 2010
1
1 Page
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
6.29 TRANSMIT CHECK SUM CONTROL REGISTER (31H).................................................................................................... 24
6.30 RECEIVE CHECK SUM CONTROL STATUS REGISTER (32H).......................................................................................... 24
6.31 EXTERNAL PHYCEIVER ADDRESS REGISTER (33H).................................................................................................... 24
6.32 GENERAL PURPOSE CONTROL REGISTER 2 (34H) ....................................................................................................... 25
6.33 GENERAL PURPOSE REGISTER 2 (35H) ....................................................................................................................... 25
6.34 GENERAL PURPOSE CONTROL REGISTER 3 (36H) ....................................................................................................... 25
6.35 GENERAL PURPOSE REGISTER 3 (37H) ....................................................................................................................... 25
6.36 PROCESSOR BUS CONTROL REGISTER (38H) .............................................................................................................. 25
6.37 INT PIN CONTROL REGISTER (39H)............................................................................................................................ 26
6.38 MONITOR REGISTER 1 (40H) ...................................................................................................................................... 26
6.39 MONITOR REGISTER 2 (41H) ...................................................................................................................................... 26
6.40 SYSTEM CLOCK TURN ON CONTROL REGISTER (50H) ............................................................................................... 26
6.41 RESUME SYSTEM CLOCK CONTROL REGISTER (51H) ................................................................................................. 26
6.42 MEMORY DATA PRE-FETCH READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F0H)............................... 26
6.43 MEMORY DATA READ COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F1H) ................................................. 27
6.44 MEMORY DATA READ COMMAND WITH ADDRESS INCREMENT REGISTER (F2H)........................................................ 27
6.45 MEMORY DATA READ ADDRESS REGISTER (F4H~F5H) .............................................................................................. 27
6.46 MEMORY DATA WRITE COMMAND WITHOUT ADDRESS INCREMENT REGISTER (F6H) ................................................ 27
6.47 MEMORY DATA WRITE COMMAND WITH ADDRESS INCREMENT REGISTER (F8H) ......................................................... 27
6.48 MEMORY DATA WRITE ADDRESS REGISTER (FAH~FBH)............................................................................................. 27
6.49 TX PACKET LENGTH REGISTER (FCH~FDH) ............................................................................................................. 27
6.50 INTERRUPT STATUS REGISTER (FEH).......................................................................................................................... 28
6.51 INTERRUPT MASK REGISTER (FFH)............................................................................................................................ 28
7. EEPROM FORMAT ........................................................................................................................................................ 29
8. MII REGISTER DESCRIPTION ................................................................................................................................... 30
8.1 BASIC MODE CONTROL REGISTER (BMCR) - 00 .......................................................................................................... 31
8.2 BASIC MODE STATUS REGISTER (BMSR) - 01 .............................................................................................................. 32
8.3 PHY ID IDENTIFIER REGISTER #1 (PHYID1) - 02 ........................................................................................................ 33
8.4 PHY ID IDENTIFIER REGISTER #2 (PHYID2) - 03 ........................................................................................................ 33
8.5 AUTO-NEGOTIATION ADVERTISEMENT REGISTER (ANAR) - 04 .................................................................................... 33
8.6 AUTO-NEGOTIATION LINK PARTNER ABILITY REGISTER (ANLPAR) – 05..................................................................... 34
8.7 AUTO-NEGOTIATION EXPANSION REGISTER (ANER) - 06 ............................................................................................. 35
8.8 DAVICOM SPECIFIED CONFIGURATION REGISTER (DSCR) - 16.................................................................................. 35
8.9 DAVICOM SPECIFIED CONFIGURATION AND STATUS REGISTER (DSCSR) - 17 ........................................................... 37
8.10 10BASE-T CONFIGURATION/STATUS (10BTCSR) - 18............................................................................................... 38
8.11 POWER DOWN CONTROL REGISTER (PWDOR) - 19 ................................................................................................... 38
8.12 (SPECIFIED CONFIG) REGISTER – 20 ............................................................................................................................ 39
9. FUNCTIONAL DESCRIPTION..................................................................................................................................... 40
9.1 HOST INTERFACE .......................................................................................................................................................... 40
9.2 DIRECT MEMORY ACCESS CONTROL ............................................................................................................................ 40
9.3 PACKET TRANSMISSION ................................................................................................................................................ 40
9.4 PACKET RECEPTION ...................................................................................................................................................... 40
9.5 100BASE-TX OPERATION ............................................................................................................................................. 40
9.5.1 4B5B Encoder ...................................................................................................................................................... 41
9.5.2 Scrambler ............................................................................................................................................................. 41
9.5.3 Parallel to Serial Converter................................................................................................................................. 41
9.5.4 NRZ to NRZI Encoder .......................................................................................................................................... 41
9.5.5 MLT-3 Converter.................................................................................................................................................. 41
9.5.6 MLT-3 Driver ....................................................................................................................................................... 41
9.5.7 4B5B Code Group ................................................................................................................................................ 42
9.6 100BASE-TX RECEIVER ............................................................................................................................................... 43
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
3
3Pages
DM9010BI
Industrial-temperature Single Chip Ethernet Controller with General Processor Interface
3. FEATURES
■ 100-pin LQFP.
■ Supports processor interface: Byte/word/Dword of
I/O command to internal memory data operation
■ Integrated 10/100M transceiver with
HP Auto-MDIX
■ Supports MII and reverses MII interface
■ Supports back pressure mode for half-duplex
mode flow control
■ IEEE802.3x flow control for full-duplex mode
■ Supports wakeup frame, link status change and
magic packet events for remote wake up
■ Integrated 16K Byte SRAM
■ Build in 3.3V to 1.8V regulator
■ Supports early Transmit
■ Supports IP/TCP/UDP checksum generation and
checking
■ Supports automatically load vendor ID and
product ID from EEPROM
■ Supports 7 or 23 GPIO pins
■ Optional EEPROM configuration
■ Very low power consumption mode:
– Power reduced mode (cable detection)
– Power down mode
– Selectable TX drivers for 1:1 or 1.25:1
transformers for additional power reduction.
– 1: 1 transformers only when HP Auto-MDIX
Enable.
■ Supports Industrial-temperature: -40 °C.~ +85°C
■ Compatible with 3.3V and 5.0V tolerant I/O
Preliminary
Version: DM9010BI--DS-P01
January 12, 2010
6
6 Page
合計 : 30 ページ |
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| 部品番号 | 部品説明 | メーカ |
| DM9010B | 10/100 MbpsSingle Chip Ethernet Controller | DAVICOM |
| DM9010BI | Industrial-temperature 10/100 MbpsSingle Chip Ethernet Controller | DAVICOM |