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DM9000BI の電気的特性と機能
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DM9000BIのメーカーはDAVICOMです、この部品の機能は「Industrial-temperature Ethernet Controller」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9000BI |
| 部品説明 Industrial-temperature Ethernet Controller |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9000BIダウンロード（pdfファイル）リンクがあります。 Total 30 pages |
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DM9000BI
Industrial-temperature Ethernet Controller with General Processor Interface
DAVICOM Semiconductor, Inc.
DM9000BI
Industrial-temperature Ethernet Controller
With General Processor Interface
DATA SHEET
Preliminary
Version: DM9000BI-13-DS-P02
March 20, 2012
Preliminary
Version: DM9000BI-DS-P02
March 20, 2012
1
1 Page
DM9000BI
Industrial-temperature Ethernet Controller with General Processor Interface
6.15 Wake Up Control Register ( 0FH ) (in 8-bit mode).................................................................................... 19
6.16 Physical Address Register ( 10H~15H ) ................................................................................................... 19
6.17 Multicast Address Register ( 16H~1DH ) .................................................................................................. 19
6.18 General purpose control Register ( 1EH ) ( For 8 Bit mode only, for 16 bit mode, see reg . 34H)...... 19
6.19 General purpose Register ( 1FH ) ( For 8 Bit mode only, for 16 bit mode, see reg . 34H)..................... 20
6.20 TX SRAM Read Pointer Address Register (22H~23H)............................................................................. 20
6.21 RX SRAM Write Pointer Address Register (24H~25H)............................................................................. 20
6.22 Vendor ID Register (28H~29H) ................................................................................................................. 20
6.23 Product ID Register (2AH~2BH) ............................................................................................................... 20
6.24 Chip Revision Register (2CH) ................................................................................................................... 20
6.25 Transmit Control Register 2 ( 2DH ).......................................................................................................... 20
6.26 Operation Test Control Register ( 2EH ) ................................................................................................... 21
6.27 Special Mode Control Register ( 2FH ) ..................................................................................................... 21
6.28 Early Transmit Control/Status Register ( 30H ) ......................................................................................... 22
6.29 Check Sum Control Register ( 31H ) ........................................................................................................ 22
6.30 Receive Check Sum Status Register ( 32H ) ............................................................................................ 22
6.31 MII PHY Address Register ( 33H ) ............................................................................................................ 23
6.32 LED Pin Control Register ( 34H ) .............................................................................................................. 23
6.33 Processor Bus Control Register ( 38H ).................................................................................................... 23
6.34 INT Pin Control Register ( 39H ) ............................................................................................................... 24
6.35 System Clock Turn ON Control Register ( 50H ) ...................................................................................... 24
6.36 Resume System Clock Control Register ( 51H )....................................................................................... 24
6.37 Memory Data Pre-Fetch Read Command without Address Increment Register (F0H) ............................ 24
6.38 Memory Data Read Command without Address Increment Register (F1H)............................................. 24
6.39 Memory Data Read Command with Address Increment Register (F2H).................................................. 24
6.40 Memory Data Read address Register (F4H~F5H) ................................................................................... 24
6.41 Memory Data Write Command without Address Increment Register (F6H) ............................................. 24
6.42 Memory data write command with address increment Register (F8H)..................................................... 25
6.43 Memory data write address Register (FAH~FBH)..................................................................................... 25
6.44 TX Packet Length Register (FCH~FDH)................................................................................................... 25
6.45 Interrupt Status Register (FEH)................................................................................................................. 25
6.46 Interrupt Mask Register (FFH) .................................................................................................................. 25
7. EEPROM Format .............................................................................................................. 26
8. PHY Register Description ............................................................................................... 27
Preliminary
Version: DM9000BI-13-DS-P02
March 20, 2012
3
3Pages
DM9000BI
Industrial-temperature Ethernet Controller with General Processor Interface
1. General Description
The DM9000BI is a fully integrated and cost-effective
Industrial-temperature low pin count single chip Fast
Ethernet controller with a general processor interface,
a 10/100M PHY and 4K Dword SRAM. It is designed
with low power and high performance process
interface that support 3.3V with 5V IO tolerance.
The DM9000BI supports 8-bit and 16-bit data
interfaces to internal memory accesses for various
processors. The PHY of the DM9000BI can interface to
the UTP3, 4, 5 in 10Base-T and UTP5 in 100Base-TX with
HP Auto-MDIX. It is fully compliant with the IEEE 802.3u
Spec. Its auto-negotiation function will automatically
configure the DM9000BI to take the maximum advantage of
its abilities. The DM9000BI also supports IEEE 802.3x full-
duplex flow control.
2. Block Diagram
LED
EEPROM
Interface
TX+/-
RX+/-
PHYceiver
100 Base-TX
transceiver
100 Base-TX
PCS
AUTO-MDIX
10 Base-T
Tx/Rx
MAC
MII
TX Machine
Control
&Status
Registers
RX Machine
Autonegotiation
MII Management
Control
& MII Register
Memory
Management
Internal
SRAM
Preliminary
Version: DM9000BI-13-DS-P02
March 20, 2012
6
6 Page
合計 : 30 ページ |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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| 部品番号 | 部品説明 | メーカ |
| DM9000B | Ethernet Controller | DAVICOM |
| DM9000BI | Industrial-temperature Ethernet Controller | DAVICOM |