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DM9301 の電気的特性と機能
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DM9301のメーカーはDAVICOMです、この部品の機能は「100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter」です。 |
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製品の詳細 ( Datasheet PDF )
| 部品番号 DM9301 |
| 部品説明 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |
| メーカ DAVICOM |
ロゴ |
このページの下部にプレビューとDM9301ダウンロード（pdfファイル）リンクがあります。 Total 22 pages |
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DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
General Description
The DM9301 is a physical-layer, single-chip, low-
power media converter for 100BASE-TX/FX full
duplex repeater applications. On the TX media side,
it provides a direct interface to Unshielded Twisted
Pair Cable 5 (UTP5) for 100BASE-TX Fast Ethernet.
On the FX media side, it provides a direct interface to
a Pseudo Emitter Coupled Logic level interface
(PECL).
The DM9301 uses a low power and high
performance CMOS process. It contains the entire
physical layer functions of 100BASE-TX as defined
by IEEE802.3u, including the Physical Coding
Sublayer (PCS), Physical Medium Attachment
(PMA), Twisted Pair Physical Medium Dependent
Sublayer (TP-PMD) and a PECL compliant interface
for a fiber optic module, compliant with ANSI X3.166.
The DM9301 provides two independent clock
Block Diagram
recovery circuits to minimize bit delay through the
converter (no FIFO are used to buffer data between
the FX and TX interfaces). Furthermore, due to the
excellent rise/fall time control by a built-in wave-
shaping filter, the DM9301 needs no external filter to
transport signals to the media on the 100Base-TX
interface.
Patent-Pending Circuits
• Smart adaptive receiver equalizer
• Digital algorithm for high frequency clock/data
recovery circuit
• High speed wave-shaping circuit
PECLSD
FXSD
RCVR
Link Status
Monitor &
LED Driver
25M FXRXCLK
125M FXRXCLK
Rise/Fall
Time
CTL
PECLRXI +/-
PECL
RCVR
25M
OSC/XTAL
RX
CRM
NRZI
to
NRZ
CGM
Serial to
Parallel
TX Code-
group
Alignment
Monitor
Scrambler
FX Code-
group
Alignment
Monitor
Parallel
to Serial
NRZ
to
NRZI
25M TPRXCLK
125M TPRXCLK
PECLTXO +/-
PECL
TXMT
NRZ
to
NRZI
Parallel
to Serial
Descrambler
Serial to
Parallel
NRZI
to
NRZ
RX
CRM
NRZI to
MLT-3
MLT-3 to
NRZI
MLT-3
Driver
Adaptive
EQ
TPTXO+/-
TPRXI+/-
Final
Version: DM9301-DS-F02
May 8, 2000
1
1 Page
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Features
• 100BASE-TX/FX single-chip media converter
• Total bit delay from FX to TX interface is 20 bit
times (10 bit times each direction).
• Optional propagate HALT on no Link condition
• Compliant with IEEE802.3u 100BASE-TX standard
• Compliant with ANSI X3T12 TP-PMD 1995
standard
• Compliant with ANSI X3.166 FDDI-PMD
• Supports Half and Full Duplex operation 100Mbps,
the DM9301 operates in Full Duplex mode at all
times
• High performance 100Mbps clock generator and
data recovery circuit
• Controlled output edge rates in the 100Base-TX
transmitter without the need for an external filter
• LED support for FX Link, TX link, FX receive data,
TX receive data, FX code group error and TX code
group error.
• Built in LED test, all LED will light during a reset
condition on the DM9301
• Digital clock recovery and regeneration circuit
using an advanced digital algorithm to minimize
jitter
• Supports diagnostic TX to TX analog loopback and
FX to FX analog loopback (Loopback at the NRZI
interface)
• Supports diagnostic TX to TX digital loopback and
FX to FX digital loopback (Loopback at the 5B
symbol interface)
• Low-power, high-performance CMOS process
• Available in a 100 QFP package
Final
Version: DM9301-DS-F02
May 8, 2000
3
3Pages
DM9301
100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter
Clock and Misc. Interface (Continued)
84 TRIDRV
I
85
RESET#
I
34
HLTNOLNK
I
93
95
LED Interface
67
64
69
CONFIGA
CONFIGB
FXLNKLED#
TXLNKLED#
FXRCVLED#
I
I
OD
OD
OD
62
TXRCVLED#
OD
80
FXERRLED#
OD
Tristate Digital Output Pins:
When set high, all digital output pins are set to high
impedance.
Reset: Active Low input that initializes the DM9301,
must be asserted low for 30msecs after VCC is stable.
Send Halt on no Link Condition:
Causes the DM9301 to Send out a Halt symbol to the
TX interface if no FX link active or send out a Halt
symbol to the FX interface if no TX link active.
Propagates a no-link condition to the Link Partner if 1,
Idle symbol if 0. Active high
Config A: Must be connected to GND
Config B: Must be connected to GND
FX Link LED:
Indicates Good Link status for 100Mbps FX operation.
Active low (Open Drain Output)
TX Link LED:
Indicates Good Link status for 100Mbps TX operation.
Active low (Open Drain Output)
FX Receive LED:
Indicates the presence of receive activity for 100Mbps
FX operation. Active low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the FXRCVLED output. This ensures that even
minimum size packets generate adequate LED ON to
insure visibility.
TX Receive LED:
Indicates the presence of receive activity for 100Mbps
TX operation. Active low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the TXRCVLED output. This ensures that even
minimum size packets generate adequate LED ON to
insure visibility.
FX Error LED:
Indicates an error was detected by the FX Code Group
Alignment Monitor function on the FX receiver. Active
low (Open Drain Output)
The DM9301 incorporates a "monostable" function on
the FXERRLED output. This ensures that even
minimum size errors generate adequate LED ON to
insure visibility.
6 Final
Version: DM9301-DS-F02
May 8, 2000
6 Page
合計 : 22 ページ |
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データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。 |
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| 部品番号 | 部品説明 | メーカ |
| DM9301 | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter | DAVICOM |
| DM9301FP | 100Mbps Ethernet Fiber/Twisted Pair Single Chip Media Converter |  Davicom |
| DM9302 | 10/100Mbps Ethernet Fiber/Twisted Pair Media Converter | DAVICOM |
| DM9308 | Dual 4-Bit Latch |  National |