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部品番号 P6NA60FP
部品説明 STP6NA60FP
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 
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P6NA60FP Datasheet, P6NA60FP PDF,ピン配置, 機能
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STP6NA60FP
N - CHANNEL ENHANCEMENT MODE
FAST POWER MOS TRANSISTOR
TYPE
STP 6NA 60F P
VDSS
600 V
RDS(on)
< 1.2
ID
3.9 A
s TYPICAL RDS(on) = 1
s ± 30V GATE TO SOURCE VOLTAGE RATING
s 100% AVALANCHE TESTED
s REPETITIVE AVALANCHE DATA AT 100oC
s LOW INTRINSIC CAPACITANCES
s GATE CHARGE MINIMIZED
s REDUCED THRESHOLD VOLTAGE SPREAD
DESCRIPTION
This series of POWER MOSFETS represents
the most advanced high voltage technology.
The optmized cell layout coupled with a new
proprietary edge termination concur to give
the device low RDS(on) and gate charge,
unequalled ruggedness and superior
switching performance.
APPLICATIONS
s HIGH CURRENT, HIGH SPEED SWITCHING
s SWITCH MODE POWER SUPPLIES (SMPS)
s DC-AC CONVERTERS FOR WELDING
EQUIPMENT AND UNINTERRUPTIBLE
POWER SUPPLIES AND MOTOR DRIVE
PRELIMINARY DATA
3
2
1
TO-220FP
INTERNAL SCHEMATIC DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
VDS Drain-source Voltage (VGS = 0)
VD GR
VGS
ID
ID
Drain- gate Voltage (RGS = 20 k)
Gate-source Voltage
Drain Current (continuous) at Tc = 25 oC
Drain Current (continuous) at Tc = 100 oC
IDM() Drain Current (pulsed)
Ptot Total Dissipation at Tc = 25 oC
Derating Factor
VISO Insulation W it hstand Voltage (DC)
Tstg St orage Temperature
Tj Max. Operating Junction Temperature
() Pulse width limited by safe operating area
October 1997
Valu e
600
600
± 30
3.9
2.6
26
40
0 .3 2
2000
-65 to 150
150
Unit
V
V
V
A
A
A
W
W/oC
V
oC
oC
1/5

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P6NA60FP pdf, 電子部品, 半導体, ピン配列
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STP6NA60FP
ELECTRICAL CHARACTERISTICS (continued)
SWITCHING ON
S ymb ol
td(on)
tr
Qg
Qgs
Qgd
P a ra m et er
Turn-on Time
Rise Time
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Test Conditions
VDD = 300 V
ID = 3 A
RG = 47
VGS = 10 V
VDD = 480 V ID = 3 A VGS = 10 V
Min.
Typ .
35
90
54
8
23
Max.
55
125
75
Unit
ns
ns
nC
nC
nC
SWITCHING OFF
S ymb ol
tr(Vo f f)
tf
tc
P a ra m et er
Off-voltage Rise Time
Fall Time
Cross-over Time
Test Conditions
VDD = 480 V ID = 6 A
RG = 47 VGS = 10 V
(see test circuit, figure 5)
Min.
Typ .
80
20
115
Max.
110
30
155
Unit
ns
ns
ns
SOURCE DRAIN DIODE
S ymb ol
P a ra m et er
Test Conditions
ISD
ISDM ()
Source-drain Current
Source-drain Current
(pulsed)
VSD () Forward On Voltage
ISD = 6.5 A VGS = 0
trr Reverse
Time
Qrr Reverse
Recovery ISD = 6 A di/dt = 100 A/µs
VDD = 100 V Tj = 150 oC
Recovery (see circuit, figure 5)
Charge
IRRM Reverse
Recovery
Current
() Pulsed: Pulse duration = 300 µs, duty cycle 1.5 %
() Pulse width limited by safe operating area
Min.
Typ .
Max.
6.5
26
Unit
A
A
1.6
600
V
ns
9 µC
30 A
3/5





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