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データシート AT24C64C PDF ダウンロード ( 特性, スペック, ピン接続図 )

部品番号 AT24C64C
部品説明 2-Wire Serial EEPROM
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 
プレビュー
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AT24C64C Datasheet, AT24C64C PDF,ピン配置, 機能
(Features
Low-voltage and Standard-voltage Operation
– 1.8 (VCC = 1.8 to 5.5V)
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bi-directional Data Transfer Protocol
1 MHz (5.0V) and 400 KHz (1.8V Compatibility)
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (5 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Lead-free/Halogen-free Devices
8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame Land Grid Array (ULA), 8-lead
TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3), and 8-ball dBGA2 Packages.
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24C32C/64C provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32C/64C is
available in space saving 8-lead PDIP, 8-lead JEDEC SOIC, 8-lead Ultra Lead Frame
Land Grid Array (ULA), 8-lead TSSOP, 8-lead Ultra Thin Mini-MAP (MLP2x3) and, 8-
ball dBGA2 packages and is accessed via a 2-wire serial interface. In addition, the
entire family is available in 1.8V (1.8 to 5.5V) version.
Pin Configurations
8-lead Ultra Thin
8-lead Ultra Lead Frame
Mini-MAP (MLP 2x3) Land Grid Array (ULA)
Pin Name
A0 - A2
SDA
Function
Address Inputs
Serial Data
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
SCL
Serial Clock Input
Bottom View
Bottom View
WP Write Protect
8-ball dBGA2
8-lead TSSOP
VCC 8
WP 7
SCL 6
SDA 5
1 A0
2 A1
3 A2
4 GND
Bottom View
8-lead SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC A0 1
7 WP
A1 2
6 SCL A2 3
5 SDA GND 4
8 VCC
7 WP
6 SCL
5 SDA
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32C
AT24C64C
Not Recommended
for New Design
5298A–SEEPR–1/08

1 Page



AT24C64C pdf, ピン配列
AT24C32C/64C
2. Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM
device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain
driven and may be wire-ORed with any number of other open-drain or open collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are
hard wired or left not connected for hardware compatibility with other AT24CXX devices. When
the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus
system (device addressing is discussed in detail under the Device Addressing section). If the
pins are left floating, the A2, A1 and A0 pins will be internally pulled down to GND if the capaci-
tive coupling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel® recommends
connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows normal write
operations. When WP is connected high to VCC, all write operations to the memory are inhibited.
If the pin is left floating, the WP pin will be internally pulled down to GND if the capacitive cou-
pling to the circuit board VCC plane is <3pF. If coupling is >3pF, Atmel recommends connecting
the pin to GND.
5298A–SEEPR–1/08
3


3Pages


AT24C64C 電子部品, 半導体
4. Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external
device. Data on the SDA pin may change only during SCL low time periods (refer to Data Valid-
ity timing diagram). Data changes during SCL high periods will indicate a start or stop condition
as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which
must precede any other command (refer to Start and Stop Definition timing diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a
read sequence, the stop command will place the EEPROM in a standby power mode (refer to
Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowl-
edge that it has received each word.
STANDBY MODE: The AT24C32C/64C features a low power standby mode which is enabled:
a) upon power-up and b) after the receipt of the Stop bit and the completion of any internal
operations.
SOFTWARE RESET: After an interruption in protocol, power loss or system reset, and 2-wire
part can be protocol reset by following these steps:
(a) Create a start bit condition, (b) clock 9 cycles, (c) create another start bit followed by stop bit
condition as shown below. The device is ready for next communication after above steps have
been completed.
Figure 4-1. Software Reset
Start bit
Dummy Clock Cycles
Start bit
Stop bit
SCL
12 3
89
SDA
6 AT24C32C/64C
5298A–SEEPR–1/08

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