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データシート TS27L2I PDF ( 特性, スペック, ピン接続図 )

部品番号 TS27L2I
部品説明 PRECISION VERY LOW POWER CMOS DUAL OPERATIONAL AMPLIFIERS
メーカ STMicroelectronics
ロゴ STMicroelectronics ロゴ 
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TS27L2I Datasheet, TS27L2I PDF,ピン配置, 機能
TS27L2C,I,M
PRECISION VERY LOW POWER
CMOS DUAL OPERATIONAL AMPLIFIERS
s VERY LOW POWER CONSUMPTION :
10µA/op
s OUTPUT VOLTAGE CAN SWING TO
GROUND
s EXCELLENT PHASE MARGIN ON
CAPACITIVE LOADS
s STABLE AND LOW OFFSET VOLTAGE
s THREE INPUT OFFSET VOLTAGE
SELECTIONS
DESCRIPTION
These devices are low cost, low power dual oper-
ational amplifiers designed to operate with single
or dual supplies. These operational amplifiers use
the ST silicon gate CMOS process allowing an ex-
cellent consumption-speed ratio. These series are
ideally suited for low consumption applications.
Three power consumptions are available allowing
to have always the best consumption-speed ratio:
u ICC = 10µA/amp.: TS27L2 (very low power)
u ICC = 150µA/amp.: TS27M2 (low power)
u ICC = 1mA/amp.: TS272 (standard)
These CMOS amplifiers offer very high input im-
pedance and extremely low input currents. The
major advantage versus JFET devices is the very
low input currents drift with temperature (see fig-
ure 2).
ORDER CODE
Part Number Temperature Range
TS27L2C/AC/BC
0°C, +70°C
TS27L2I/AI/BI
-40°C, +125°C
TS27L2M/AM/BM
-55°C, +125°C
Example : TS27L2ACN
Package
NDP
•••
•••
•••
N = Dual in Line Package (DIP)
D = Small Outline Package (SO) - also available in Tape & Reel (DT)
P = Thin Shrink Small Outline Package (TSSOP) - only available
in Tape & Reel (PT)
N
DIP8
(Plastic Package)
D
SO8
(Plastic Micropackage)
P
TSSOP8
(Thin Shrink Small Outline Package)
PIN CONNECTIONS (top view)
1
2-
3+
4
8
7
-6
+5
1 - Output 1
2 - Inverting Input 1
3 - Non-inverting Input 1
4 - V CC -
5 - Non-inverting Input 2
6 - Inverting Input 2
7 - Output 2
8 - V CC +
November 2001
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TS27L2I pdf, ピン配列
SCHEMATIC DIAGRAM (for 1/2 TS27L2)
TS27L2C,I,M
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TS27L2I 電子部品, 半導体
TS27L2C,I,M
Figure 5 : Open Loop Frequency Response and
Phase Shift
Figure 8 : Phase Margin versus Capacitive Load
50
40
30
PHASE
2 0 Tamb = 2 5 °C
10
V
+
CC
=
10V
R L = 1M
0
C L = 100pF
A VCL = 1 0 0
-10
G AIN
Phase
Margin
Gain
Bandwidth
Product
0
45
90
135
180
2
10
3
10
4
10
5 67
10 10 10
FREQ UENCY, f (Hz)
Figure 6 : Gain Bandwidth Product versus Supply
Voltage
120
100
80
T amb = 2 5 °C
R L = 1M
C L = 100pF
AV = 1
80
T amb = 2 5 °C
RL = 1M
70 A V = 1
V CC= 1 0 V
60
50
40
0
20 40 60 80
C APAC ITAN C E, C L (pF)
100
Figure 9 : Slew Rate versus Supply Voltage
0.05
0.04
T amb = 2 5 °C
RL = 1M
C L = 100pF
SR
60
40
0 4 8 12 16
S U P P L Y V O L T A G E , VCC (V )
Figure 7 : Phase Margin versus Supply Voltage
0.03
SR
0.02
4
6 8 10 12 14
S U P P L Y V O L T A G E , VCC (V )
16
Figure 10 : Input Voltage Noise versus
Frequency
60
T amb = 2 5 °C
R L = 1M
50
C = 100pF
A
L
V
=
1
300
200
VCC = 1 0 V
Tamb= 2 5 °C
R S= 1 0 0
40
100
30
04
8 12
S U P P L Y V O L T A G E , V CC (V )
16
0
1
10
100
1000
FREQ UENCY (Hz)
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