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データシート AT24C64 PDF ( 特性, スペック, ピン接続図 )

部品番号 AT24C64
部品説明 2-Wire Serial EEPROM
メーカ ATMEL Corporation
ロゴ ATMEL Corporation ロゴ 
プレビュー
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AT24C64 Datasheet, AT24C64 PDF,ピン配置, 機能
Features
Low-Voltage and Standard-Voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Low-Power Devices (ISB = 2 µA at 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
2-Wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate
Write Protect Pin for Hardware Data Protection
32-Byte Page Write Mode (Partial Page Writes Allowed)
Self-Timed Write Cycle (10 ms max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Grade and Extended Temperature Devices Available
8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC,
and 8-pin TSSOP Packages
Description
The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and pro-
grammable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common 2-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32/64 is
available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC,
and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface.
In addition, the entire family is available in 2.7V (2.7V to 5.5V) and 1.8V (1.8V to 5.5V)
versions.
2-Wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32
AT24C64
Pin Configurations
Pin Name
A0 - A2
SDA
SCL
WP
Function
Address Inputs
Serial Data
Serial Clock Input
Write Protect
8-Pin PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin TSSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-Pin SOIC
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
2-Wire, 32K
Serial E2PROM
Rev. 0336K–SEEPR–7/03
1

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AT24C64 pdf, ピン配列
AT24C32/64
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address
inputs that are hard wired or left not connected for hardware compatibility with
AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0
are zero.
WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write
operations. When WP is tied high to VCC, all write operations to the upper quandrant
(8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to
GND.
Memory Organization AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256
pages of 32 bytes each. Random word addressing requires a 12/13 bit data word
address.
0336K–SEEPR–7/03
3


3Pages


AT24C64 電子部品, 半導体
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (refer to Start and Stop Definition timing
diagram).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (refer to Start and Stop Definition timing diagram).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the
EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32/64 features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion
of any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-
wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6 AT24C32/64
0336K–SEEPR–7/03

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