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部品番号 ASM3P2775A
部品説明 Low Power Peak EMI Reducing Solution
メーカ PulseCore Semiconductor
ロゴ PulseCore Semiconductor ロゴ 
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ASM3P2775A Datasheet, ASM3P2775A PDF,ピン配置, 機能
November 2006
rev 0.3
Low Power Peak EMI Reducing Solution
ASM3P2775A
Features
Generates an EMI optimized clock signal at the
output.
Integrated loop filter components.
Operates with a 3.3V Supply.
Operating current less than 4mA.
Low power CMOS design.
Input frequency range: 13MHz to 30MHz
Generates a 1X low EMI spread spectrum clock
of the input frequency.
Frequency deviation: ±1.75% (Typ) @14.7MHz
Input Frequency.
Available in 6-pin TSOT-23, 8-pin SOIC and 8-
pin TSSOP packages.
Product Description
The ASM3P2775A is a versatile spread spectrum
frequency modulator designed specifically for a wide
range of clock frequencies. The ASM3P2775A reduces
electromagnetic interference (EMI) at the clock source,
allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2775A allows significant
system cost savings by reducing the number of circuit
board layers, ferrite beads and shielding that are
traditionally required to pass EMI regulations.
The ASM3P2775A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented by using a proprietary all digital method.
The ASM3P2775A modulates the output of a single PLL
in order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal produced
by oscillators and most frequency generators. Lowering
EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation’.
Applications
The ASM3P2775A is targeted towards all portable
devices with very low power requirements like MP3
players and digital still cameras.
Key Specifications
Description
Supply voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency Deviation
Specification
VDD = 3.3V ± 0.3V
200pS (Max)
45/55% (worst case)
FIN/640
±1.75% (Typ) @ 14.7MHz
Block Diagram
VDD
PD
XIN/CLKIN
XOUT
Crystal
Oscillator
Frequency
Divider
Feedback
Divider
Modulation
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008 Tel: 408-879-9077 Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.

--------------------------------------------
ASM3P2775A pdf, 電子部品, 半導体, ピン配列
November 2006
rev 0.3
Modulation Profile
ASM3P2775A
Specifications
Description
Frequency Range
Modulation Equation
Frequency Deviation
Specification
13MHz < CLKIN < 30MHz
FIN/640
±1.75% (Typ) @ 14.7MHz
Absolute Maximum Ratings
Symbol
VDD, VIN
TSTG
TA
Ts
TJ
TDV
Parameter
Voltage on any pin with respect to Ground
Storage temperature
Operating temperature
Max. Soldering Temperature (10 sec)
Junction Temperature
Static Discharge Voltage
(As per JEDEC STD22- A114-B)
Rating
-0.5 to +4.6
-65 to +125
-40 to +85
260
150
2
Unit
V
°C
°C
°C
°C
KV
Note: These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Power Peak EMI Reducing Solution
Notice: The information in this document is subject to change without notice.
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