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部品番号 ASM3P2760A
部品説明 Peak EMI Reducing Solution
メーカ ON Semiconductor
ロゴ ON Semiconductor ロゴ 
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ASM3P2760A Datasheet, ASM3P2760A PDF,ピン配置, 機能
ASM3P2760A
Peak EMI Reducing Solution
Product Description
The ASM3P2760A is a versatile spread spectrum frequency
modulator designed specifically for a wide range of clock frequencies.
The ASM3P2760A reduces electromagnetic interference (EMI) at the
clock source, allowing system wide reduction of EMI of all clock
dependent signals. The ASM3P2760A allows significant system cost
savings by reducing the number of circuit board layers, ferrite beads
and shielding that are traditionally required to pass EMI regulations.
The ASM3P2760A uses the most efficient and optimized
modulation profile approved by the FCC and is implemented by using
a proprietary all digital method.
The ASM3P2760A modulates the output of a single PLL in order to
“spread” the bandwidth of a synthesized clock, and more importantly,
decreases the peak amplitudes of its harmonics. This results in
significantly lower system EMI compared to the typical narrow band
signal produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called ‘spread
spectrum clock generation.’
Features
Generates an EMI Optimized Clock Signal at the Output
Integrated Loop Filter Components
Operates with a 2.5/3.3 V Supply
Operating Current less than 4 mA
CMOS Design
Input Frequency Range:
6 MHz to 12 MHz for 2.5 V
6 MHz to 13 MHz for 3.3 V
Generates a 1x Low EMI Spread Spectrum Clock of the Input
Frequency
Frequency Deviation: ±0.65% @ 8 MHz
Available in TSOP−6 Package
This Device is Pb-Free and is RoHS Compliant
Applications
The ASM3P2760A is targeted towards all portable devices like
MP3 players and digital still cameras.
Table 1. KEY SPECIFICATIONS
Description
Supply Voltages
Cycle-to-Cycle Jitter
Output Duty Cycle
Modulation Rate Equation
Frequency Deviation
Specification
VDD = 2.5/3.3 V
±200 ps (Typ)
45/55%
FIN/256
±0.65% @ 8 MHz
www.onsemi.com
1
TSOP−6
CASE 318G
PIN CONNECTION
PD 1
6 VSS
XOUT 2 ASM3P2760A 5 ModOUT
XIN/CLKIN 3
4 VDD
MARKING DIAGRAM
E4LAYWG
G
1
E4L = Specific Device Code
A = Assembly Location
Y = Year
W = Work Week
G = Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information on page 6 of
this data sheet.
© Semiconductor Components Industries, LLC, 2015
July, 2015 − Rev. 3
1
Publication Order Number:
ASM3P2760/D

--------------------------------------------
ASM3P2760A pdf, 電子部品, 半導体, ピン配列
ASM3P2760A
Table 4. RECOMMENDED OPERATING CONDITIONS
Parameter
Description
Min Max Unit
VDD
Supply Voltage
2.375
3.6
V
TA Operating Temperature (Ambient Temperature)
0 70 °C
CL Load Capacitance
− 15 pF
CIN Input Capacitance
− 7 pF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
Table 5. DC ELECTRICAL CHARACTERISTICS FOR 2.5 V SUPPLY
Symbol
Parameter
Min Typ Max Unit
VIL Input Low Voltage
VSS − 0.3
0.8 V
VIH Input High Voltage
2.0
VDD + 0.3
V
IIL Input Low Current
− − −35 mA
IIH Input High Current
− − 35 mA
IXOL
XOUT Output Low Current (@ 0.5 V, VDD = 2.5 V)
− 3 − mA
IXOH
XOUT Output High Current (@ 1.8 V, VDD = 2.5 V)
− 3 − mA
VOL Output Low Voltage (VDD = 2.5 V, IOL = 8 mA)
− − 0.6 V
VOH Output High Voltage (VDD = 2.5 V, IOH = 8 mA)
1.8 −
−V
IDD Static Supply Current (Note 1)
− − 10 mA
ICC Dynamic Supply Current (2.5 V, 8 MHz and No Load)
2.5 mA
VDD Operating Voltage
2.375 2.5 2.625 V
tON Power-Up Time (First Locked Cycle after Power-Up) (Note 2)
5 ms
ZOUT
Output Impedance
− 50 − W
1. XIN/CLKIN pin and PD pin are pulled low.
2. VDD and XIN/CLKIN input are stable, PD pin is made high from low.
Table 6. AC ELECTRICAL CHARACTERISTICS FOR 2.5 V SUPPLY
Symbol
Parameter
CLKIN Input Frequency
ModOUT Output Frequency
fD Frequency Deviation
Input Frequency = 6 MHz
Input Frequency = 12 MHz
tLH* Output Rise Time (Measured at 0.7 V to 1.7 V)
tHL* Output Fall Time (Measured at 1.7 V to 0.7 V)
tJC Jitter (Cycle-to-Cycle)
tD Output Duty Cycle
* tLH and tHL are measured into a capacitive load of 15 pF.
Min
6
6
0.4
0.4
45
Typ
±1.0
±0.45
1.2
0.9
±200
50
Max Unit
12 MHz
12 MHz
%
1.4 ns
1.1 ns
− ps
55 %
www.onsemi.com
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