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データシート HCPL-0723 PDF ( 特性, スペック, ピン接続図 )

部品番号 HCPL-0723
部品説明 50 MBd 2 ns PWD High Speed CMOS Optocoupler
メーカ Avago
ロゴ Avago ロゴ 
プレビュー
Total 12 pages
		
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HCPL-0723 Datasheet, HCPL-0723 PDF,ピン配置, 機能
HCPL-7723/0723
50 MBd 2 ns PWD High Speed CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either 8-pin DIP or SO‑8 package style respec-
tively, the HCPL-7723 or HCPL-0723 optocoupler utilize
the latest CMOS IC technology to achieve outs­tanding
speed performance of minimum 50 MBd data rate and
2 ns maximum pulse width distortion.
Basic building blocks of HCPL-7723/0723 are a CMOS
LED driver IC, a high speed LED and a CMOS detector
IC. A CMOS logic input signal controls the LED driver
IC, which supplies current to the LED. The detector
IC incorporates an integrated photodiode, a high speed
transimpedance amplifier, and a voltage comparator with
an output driver.
Functional Diagram
**VDD1 1
8 VDD2**
Features
• +5 V CMOS compatibility
• High speed: 50 MBd min.
• 2 ns max. pulse width distortion
• 22 ns max. prop. delay
• 16 ns max. prop. delay skew
• 10 kV/µs min. common mode rejection
• –40 to 85°C temperature range
• Safety and regulatory approvals:
UL recognized
– 5000 Vrms for 1 min. per UL1577 for HCPL-7723 for
option 020
– 3750 Vrms for 1 min. per UL1577 for HCPL-0723
CSA component acceptance notice #5
IEC/EN/DIN EN 60747-5-5
– Viorm = 630 Vpeak for HCPL-7723   option 060
– Viorm = 567 Vpeak for HCPL-0723   option 060
VI 2
NC* 3
GND1 4
LED1
SHIELD
7 NC*
IO
6 VO
5 GND2
* PIN 3 IS THE ANODE OF THE INTERNAL LED AND MUST BE LEFT
UNCONNECTED FOR GUARANTEED DATASHEET PERFORMANCE.
PIN 7 IS NOT CONNECTED INTERNALLY.
** A 0.1 µF BYPASS CAPACITOR MUST BE CONNECTED BETWEEN
PINS 1 AND 4, AND 5 AND 8.
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
H
L
LED1
OFF
ON
VO, OUTPUT
H
L
Applications
• Digital fieldbus isolation: CC-Link, DeviceNet, Profibus,
SDS, Isolated A/D or D/A conversion
• Multiplexed data transmission
• High speed digital input/output
• Computer peripheral interface
• Microprocessor system interface
CAUTION: It is advised that normal static precautions be taken in handling and assembly of
this component to prevent damage and/or degradation, which may be induced by ESD.

1 Page



HCPL-0723 pdf, ピン配列
HCPL-7723 Package with Gull Wing Surface Mount Option 300
9.65 ± 0.25
(0.380 ± 0.010)
LAND PATTERN RECOMMENDATION
1.016 (0.040)
87
65
6.350 ± 0.25
(0.250 ± 0.010)
10.9 (0.430)
12
34
1.27 (0.050)
2.0 (0.080)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
3.56 ± 0.13
(0.140 ± 0.005)
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
(00..205140++--0000...0.00005072136))
1.080 ± 0.320
(0.043 ± 0.013)
2.54
(0.100)
0.635 ± 0.130
(0.025 ± 0.005)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
HCPL-0723 Small Outline SO-8 Package
0.635 ± 0.25
(0.025 ± 0.010)
12° NOM.
LAND PATTERN RECOMMENDATION
3.937 ± 0.127
(0.155 ± 0.005)
8765
XXXV
YWW
5.994 ± 0.203
(0.236 ± 0.008)
TYPE NUMBER
(LAST 3 DIGITS)
DATE CODE
PIN ONE 1 2 3 4
0.406 ± 0.076
(0.016 ± 0.003)
1.270
(0.050)
BSC
* 5.080 ± 0.127
(0.200 ± 0.005)
7.49 (0.295)
1.9 (0.075)
0.64 (0.025)
45° X
0.432
(0.017)
3.175 ± 0.127
(0.125 ± 0.005)
1.524
(0.060)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
5.207 ± 0.254 (0.205 ± 0.010)
0.203 ± 0.102
0.305
(0.012)
MIN.
(0.008 ± 0.004)
DIMENSIONS IN MILLIMETERS (INCHES). LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
3


3Pages


HCPL-0723 電子部品, 半導体
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimensions are needed as a starting point for the
equipment designer when determining the circuit insula-
tion requirements. However, once mounted on a printed
circuit board, minimum creepage and clearance require-
ments must be met as specified for individual equipment
standards. For creepage, the shortest distance path along
the surface of a printed circuit board between the solder
fillets of the input and output leads must be considered.
There are recommended techniques such as grooves
and ribs, which may be used on a printed circuit board
to achieve desired creepage and clearances. Creepage
and clearance distances will also change depending
on factors such as pollution degree and insulation
level.
IEC/EN/DIN EN 60747-5-5 Insulation Characteristics (Option 060)
Characteristic
Description
Symbol HCPL-7723 HCPL-0723 Unit
Installation classification per DIN VDE 0110, Table 1
for rated mains voltage 150 Vrms
for rated mains voltage 300 Vrms
for rated mains voltage 600 Vrms
Climatic Classification
Pollution Degree (DIN VDE 0110/39)
Maximum Working Insulation Voltage
Input to Output Test Voltage, Method b*
VIORM
I – IV
I – III
I – IV
55/85/21
2
630
I – IV
I – III
I – III
55/85/21
2
567
Vpeak
VIORM x 1.875 = VPR, 100% Production Test with tm=1 sec,
Partial discharge < 5 pC
VPR
1181
1063
Vpeak
Input to Output Test Voltage, Method a*
VIORM x 1.6 = VPR, Type and Sample Test, tm=10 sec, Partial discharge < 5 pC
Highest Allowable Overvoltage (Transient Overvoltage tini = 60 sec)
Safety-limiting values – maximum values allowed in the event of a failure
VPR
VIOTM
1008
8000
907
6000
Vpeak
Vpeak
Case Temperature
Input Current
Output Power
Insulation Resistance at TS, VIO = 500 V
TS
IS, INPUT
PS, OUTPUT
RS
175
230
600
109
150
150
600
109
°C
mA
mW
*Refer to the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/EN/
DIN EN 60747-5-5, for a detailed description of Method a and Method b partial discharge test profiles.
6

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