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データシート AT24C64A PDF ダウンロード ( 特性, スペック, ピン接続図 )

部品番号 AT24C64A
部品説明 Two-wire Serial EEPROM
メーカ ATMEL
ロゴ ATMEL ロゴ 
プレビュー
Total 22 pages
		
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AT24C64A Datasheet, AT24C64A PDF,ピン配置, 機能
Features
Low-Voltage and Standard-Voltage Operation
– 2.7 (VCC = 2.7V to 5.5V)
– 1.8 (VCC = 1.8V to 5.5V)
Low-Power Devices (ISB = 6 µA @ 5.5V) Available
Internally Organized 4096 x 8, 8192 x 8
Two-wire Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400 kHz (1.8V, 2.5V, 2.7V, 5V) Compatibility
Write Protect Pin for Hardware Data Protection
32-byte Page Write Mode (Partial Page Writes Allowed)
Self-timed Write Cycle (5 ms Max)
High Reliability
– Endurance: 1 Million Write Cycles
– Data Retention: 100 Years
Automotive Devices Available
8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ SOIC, 8-lead Mini-MAP (MLP 2x3)
and 8-lead TSSOP Packages
Lead-free/Halogen-free
Die Sales: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The AT24C32A/64A provides 32,768/65,536 bits of serial electrically erasable and
programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits
each. The device’s cascadable feature allows up to 8 devices to share a common two-
wire bus. The device is optimized for use in many industrial and commercial applica-
tions where low power and low voltage operation are essential. The AT24C32A/64A is
available in space saving 8-lead JEDEC PDIP, 8-lead JEDEC SOIC, 8-lead EIAJ
SOIC, 8-lead Mini-MAP (MLP 2x3) and 8-lead TSSOP packages and is accessed via
a 2-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V)
and 1.8V (1.8V to 5.5V) versions.
Two-wire
Serial EEPROM
32K (4096 x 8)
64K (8192 x 8)
AT24C32A(1)
AT24C64A(2)
Notes: 1. Not recommended for
new design; please
refer to AT24C32C.
2. Not recommended for
new design; please
refer to AT24C64C.
Table 1. Pin Configuration
Pin Name Function
A0 – A2
Address Inputs
SDA
Serial Data
SCL Serial Clock Input
WP Write Protect
8-lead SOIC
8-lead Mini-MAP (MLP 2x3)
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
VCC
WP
SCL
SDA
8
7
6
5
1 A0
2 A1
3 A2
4 GND
Bottom View
8-lead TSSOP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
8-lead PDIP
A0
A1
A2
GND
1
2
3
4
8 VCC
7 WP
6 SCL
5 SDA
3054T–SEEPR–1/07
1

1 Page



AT24C64A pdf, ピン配列
AT24C32A/64A
Pin Description
SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each
EEPROM device and negative edge clock data out of each device.
SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is
open-drain driven and may be wire-ORed with any number of other open-drain or open
collector devices.
DEVICE/ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs
that are hardwired or left not connected for hardware compatibility with other AT24Cxx
devices. When the pins are hardwired, as many as eight 32K/64K devices may be
addressed on a single bus system (device addressing is discussed in detail under the
Device Addressing section). If the pins are left floating, the A2, A1 and A0 pins will be
internally pulled down to GND if the capacitive coupling to the circuit board VCC plane is
<3 pF. If coupling is >3 pF, Atmel recommends connecting the address pins to GND.
WRITE PROTECT (WP): The write protect input, when connected to GND, allows nor-
mal write operations. When WP is connected high to VCC, all write operations to the
memory are inhibited. If the pin is left floating, the WP pin will be internally pulled down
to GND if the capacitive coupling to the circuit board VCC plane is <3 pF. If coupling is
>3 pF, Atmel recommends connecting the pin to GND. Switching WP to VCC prior to a
write operation creates a software write protect function.
Memory Organization AT24C32A/64A, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as
128/256 pages of 32 bytes each. Random word addressing requires a 12/13-bit data
word address.
3054T–SEEPR–1/07
3


3Pages


AT24C64A 電子部品, 半導体
Device Operation
CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an exter-
nal device. Data on the SDA pin may change only during SCL low time periods (refer to
Data Validity timing diagram). Data changes during SCL high periods will indicate a start
or stop condition as defined below.
START CONDITION: A high-to-low transition of SDA with SCL high is a start condition
which must precede any other command (see Figure 5 on page 8).
STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition.
After a read sequence, the stop command will place the EEPROM in a standby power
mode (see Figure 5 on page 8).
ACKNOWLEDGE: All addresses and data words are serially transmitted to and from
the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to
acknowledge that it has received each word.
STANDBY MODE: The AT24C32A/64A features a low power standby mode which is
enabled: a) upon power-up and b) after the receipt of the stop bit and the completion of
any internal operations.
MEMORY RESET: After an interruption in protocol, power loss or system reset, any
two-wire part can be reset by following these steps:
(a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then
(c) create a start condition as SDA is high.
6 AT24C32A/64A
3054T–SEEPR–1/07

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