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電子部品 AT24C64D Datasheet 詳細情報 ( 特性, スペック, ピン接続図 )

部品番号 AT24C64D
部品説明 I2C-Compatible (2-Wire) Serial EEPROM
メーカ ATMEL
ロゴ ATMEL ロゴ 
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AT24C64D Datasheet, AT24C64D PDF,ピン配置, 機能
AT24C64D
I2C-Compatible (2-Wire) Serial EEPROM
64-Kbit (8,192 x 8)
DATASHEET
Features
Low-voltage and Standard-voltage Operation
̶ VCC = 1.7V to 5.5V
Internally Organized as 8,192 x 8 (64K)
I2C-compatible (2-Wire) Serial Interface
Schmitt Trigger, Filtered Inputs for Noise Suppression
Bidirectional Data Transfer Protocol
400kHz (1.7V) and 1MHz (2.5V, 2.7V, 5.0V) Compatibility
Write Protect Pin for Hardware Protection
32-byte Page Write Mode
̶ Partial Page Writes Allowed
Self-timed Write Cycle (5ms Max)
High Reliability
̶ Endurance: 1,000,000 Write Cycles
̶ Data Retention: 100 Years
Lead-free/Halogen-free Devices Available
Green Package Options (Pb/Halide-free/RoHS Compliant)
̶ 8-lead JEDEC SOIC, 8-lead TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball
VFBGA, and 4-ball/5-ball/6-ball WLCSP Packages
Die Sale Options: Wafer Form, Waffle Pack, and Bumped Wafers
Description
The Atmel® AT24C64D provides 65,536-bits of Serial Electrically Erasable and
Programmable Read-Only Memory (EEPROM) organized as 8,192 words of 8 bits
each. The device’s cascading feature allows up to eight devices to share a
common 2-wire bus. The device is optimized for use in many industrial and
commercial applications where low-power and low-voltage operation are
essential. The devices are available in space-saving 8-lead JEDEC SOIC, 8-lead
TSSOP, 8-pad UDFN, 8-pad XDFN, 8-ball VFBGA, and 4-ball/5-ball/6-ball
WLCSP packages. In addition, this device operates from 1.7V to 5.5V.
Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015

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AT24C64D pdf, 電子部品, 半導体, ピン配列
3. Block Diagram
VCC
GND
WP
SCL
SDA
A2
A1
A0
Start
Stop
Logic
LOAD
Device
Address
Comparator
R/W
Serial
Control
Logic
COMP
LOAD INC
Data Word
Addr/Counter
EN H.V. Pump/Timing
Data Recovery
EEPROM
DIN
DOUT
Y DEC
Serial MUX
DOUT/ACK
LOGIC
4. Pin Descriptions
Serial Clock (SCL): The SCL input is used to positive-edge clock data into each EEPROM device and negative-
edge clock data out of each device.
Serial Data (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open drain driven and may be
wire-ORed with any number of other open-drain or open-collector devices.
Device Addresses (A2, A1, A0): The A2, A1, and A0 pins are device address inputs that are hard wired (directly to
GND or to VCC) for compatibility with other Atmel AT24C devices. When the pins are hard wired, as many as eight
64K devices may be addressed on a single bus system. (Device addressing is discussed in detail in Section 7.,
“Device Addressing” on page 9). A device is selected when a corresponding hardware and software match is true.
If these pins are left floating, the A2, A1, and A0 pins will be internally pulled down to GND. However, due to
capacitive coupling that may appear during customer applications, Atmel recommends always connecting the
address pins to a known state. When using a pull-up resistor, Atmel recommends using 10kor less.
Write Protect (WP): The Write Protect input, when connected to GND, allows normal Write operations. When WP
is connected directly to VCC, all Write operations to the memory are inhibited. If the pin is left floating, the WP pin
will be internally pulled down to GND: however, due to capacitive coupling that may appear during customer
applications, Atmel recommends always connecting the WP pins to a known state. When using a pull-up resistor,
Atmel recommends using 10kor less.
Table 4-1. Write Protect
WP Pin Status
At VCC
At GND
Part of the Array Protected
Full Array
Normal Read/Write Operations
AT24C64D [DATASHEET]
Atmel-8850D-SEEPROM-AT24C64D-Datasheet_052015
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